Capacitor matching influences linearity performance, which is a critical measure of analog-to-digital converters (ADCs). Various placement techniques have been proposed to eliminate both systematic and random mismatches of capacitor pairs. However, a placement technique that eliminates capacitor mismatches may not result in good linearity performance for successive-approximation-register ADCs because their linearity performance is related to the accuracy of their binary-weighted continued ratio. This paper addresses the critical problem of placement estimation based on ratio mismatch M, overall correlation coefficient L, and performance metrics. A low M and a high L value do not imply higher linearity performance. Therefore, we propose a partition-centering-based symmetry placement algorithm for the layout considering parasitic capacitance matching. The experimental results show that the proposed placement approach can achieve higher linearity performance and a shorter placement generation time compared with the conventional approach.

The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratio mismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.

This paper presents a dual-level dual-phase pulse-width modulation (DLDP PWM) Class-D audio amplifier circuit which enhance amplifier linearity and reduce distortion. The proposed DLDP PWM Class-D audio amplifier includes two sets of non-overlapping triangular waves, each at its respectful offset levels. Each set of triangular waves is composed of two 180° out-of-phase triangular waves. The differential power stage consists of 8 power transistors, with voltage swings up to +/- 6V. Simulated results shows that the proposed DLDP PWM Class-D audio amplifier features an SNR up to 105 dB, and the THD is suppressed below 0.001 %, with the 3rd harmonic below -102 dBV.

This paper presents the first-ever single-inductor programmable-output (SIPO) DC-DC Converters. A SIPO converter is comprised of a DC-DC converter and a Phase-locked Loop (PLL). Based on the input frequency generated internally, the PLL provides the reference voltage for the converter to generate the desired voltage levels. To demonstrate the SIPO design concept, a voltage-mode boost DC-DC converter with a constant duty-cycle pulse control technique is implemented. For an input voltage of 1.5V, the boost converter is programmed to boost the output voltages to 2V to 4V over 90% power efficiency for the load currents ranged from 50mA to 300mA.

Yield is defined as the probability that the circuit under consideration meets with the design specification within the tolerance. Placement with higher correlation coefficients has fewer mismatches and lower variation of capacitor ratio, thus achieving higher yield performance. This study presents a new optimization criterion that quickly determines if the placement is optimal. The optimization criterion leads to the development of the concepts of C-entries and partitioned subarrays which can significantly reduce the searching space for finding the optimal/near-optimal placements on a sufficiently large array size.

This paper presents a novel 2/3 divider cell circuit design for a truly modular programmable frequency divider with high-speed, low-power, and high input-sensitivity features. In this paper, the proposed flip-flop based 2/3 divider cell adopts dynamic E-TSPC circuit that not only reduces power consumption, but also improves operation speed and input sensitivity. The whole design was implemented using the TSMC 0.18 μm 1P6M CMOS process. With an 8-stage 2/3 divider cell, the measurement results indicate that the proposed circuit operates up to 5.8 GHz with the power-consumption less than 3.24 mW.

This paper describes and resolves the false locking issue in phase-locked loops (PLLs) with π-phase detector. In order to verify the proposed approach for acquisition and capture range performances of π-phase detector, the phase-controlled-current-source (PCCS) using the reversing scheme is implemented in TSMC 0.18μm 1P6M CMOS technology. In the simulation results, the locking time of the proposed approach is 6.7X faster than conventional PFD design. Moreover, the measurement results indicate the locking time of testing PLL is less than 2μs.

Capacitor mismatch can generally result from two sources of error: random mismatch and systematic mismatch. Random mismatch is caused by process variation, while systematic mismatch is mainly due to an asymmetrical layout and processing gradients. A common centroid structure may be used to reduce systematic mismatch errors, but not random mismatch errors. Based on the spatial correlation model, this paper formulates the placement optimization problem of analog circuits using switched-capacitor techniques. A placement with higher correlation coefficients of the unit capacitors results in a higher acceptance rate, or chip yield. This paper proposes a heuristic algorithm that quickly and automatically derives the placement of the unit capacitors with the highest, or near-highest, correlation coefficients for yield improvement. Results show that the resultant placement derived from the proposed algorithm achieves better yield improvement than that from a common centroid approach. The proposed heuristic algorithm can be applied for any arbitrary capacitor ratios, i.e., more than two capacitors.

A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. A multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with eleven SoC projects sharing the common platform. The total silicon area is about 37.97 mm2in the TSMC 0.13 um CMOS generic logic process technology. Compared with the total chip area 129.39 mm2by implementing these projects separately, the results show that there are 91.42 mm2silicon areas reduced by the MP-SoC platform. In order to verify MP-SoC through silicon prototyping, a system modeling and hardware/ software co-design virtual platform were implemented. A configurable SoC prototyping system, namely CONCORD, is also created as a verification platform for emulating the hardware of MP-SoC before chip being taped out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems.

This paper presents a Programmable SoC (System- on-chip) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. Results show that an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03mm , while the area of the integrated platform is about 24.43mm . The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13um CMOS generic logic process technology.

Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market.

In this paper, the content-based retrieval of audio example based on MP3 digital music archive is considered. In our proposed method, the sub-band coefficients (SBC) in a MP3 frame is used for feature extraction. Both quantization-tree indexing (QT) approach and the melody-line tracking (MLT) approach are proposed for indexing MP3 objects. Finally, a two-stage comparison method is used to measure the similarity between MP3 objects. We also employ the measurement of the similarity between query sample and database items. Evaluations on a content-based MP3 retrieval system are performed. Experimental results show that our proposed approach can achieve good performance and high accuracy

Previous work on extreme-voltage stress test of analog ICs has suffered either from time-costly circuit-level simulation or from the considerable number of bits in the control signal added to circuit for stress operation. This paper presents several fully-stressable circuit structures the appropriate use of which in analog ICs eliminates the need for extra control bits. Based on proposed circuit concepts an operational amplifier is designed in TSMC 0.18µm CMOS technology and is simulated with HSPICE. Simulation results have shown that the designed operational amplifier is fully stressable with minor performance degradation.

Memory cores are usually the densest portion with the smallest feature size in system-on-chip (SOC) designs. The reliability of memory cores thus has a heavy impact on the reliability of SOCs. The transparent test is a useful technique for improving the reliability of memories during their life time. The paper presents a systematic algorithm used for transforming a bit-oriented march test into a transparent word-oriented march test. The transformed transparent march test has shorter test complexity compared with those proposed previously (Nicolaidis, M., IEEE Trans. Computers, vol.45, no.10, p.1141-56, 1996; Thaller, K. and Steininger, A., IEEE Trans. Reliability, vol.52, no.4, p.413-22, 2003). For example, if a memory with 32-bit words is tested with March C-, the time complexity of the transparent word-oriented test transformed by the proposed scheme is only about 56% and 19% of the time complexity of the transparent word-oriented test converted by the schemes reported by Nicolaidis and by Thaller and Steininger, respectively.

With the successful development of EVoSTA (Extreme-Voltage Stress Test for Analog CMOS ICs), this paper investigated whether the extreme-temperature burn-in stress test is properly applied for enhancing the gate-oxide reliability of mixed-signal/analog CMOS ICs. Burn-in is an effective screening method used in predicting, achieving, and enhancing field reliability of ICs. Today, almost all IC manufacturers perform 100% burn-in for various durations to screen defective products. However, the major problems associated with burn-in are the determination of exactly how long the burn-in process should continue, balancing appropriately the needs of reliability and the total costs, and what stress vectors should be applied? This paper conducted a feasibility study for resolving such issues.

Series resistance associated with inductor is usually ignored in noise optimization for CMOS low noise amplifiers (LNAs). With low-quality on-chip inductor the series resistance, however, degrades input matching and increases noise figure considerably. The LNA design is complicated by the fact that the series resistance varies with inductance in some specific pattern determined by physical implementation for on-chip inductor. This paper presents a novel noise optimization technique for the codesign of LNA and low-quality square spiral inductor. Theoretical derivation is given to model the tradeoff between thermal noise of series resistance and transistor channel noise for minimizing noise figure. A figure-of-merit (FOM) is proposed to characterize the relation between qual-ity factor and effective inductance for square spiral inductor. The codesign of LNA and inductor is done by performing noise op-timization for constant FOM. Design procedure is developed and validated by post-layout simulation in AMI 0.6um CMOS process with Cadence SpectreRF and Berkeley ASITIC tools.

Yield and reliability are two factors affecting the profitability of semiconductor manufacturing. High-temperature burn-in and extreme-voltage stress tests are two current industrial standard methods to speed up the deterioration of electronic devices and weed-out infant mortality. Extreme-voltage stress test aims at enhancing both quality and reliability without performance the high-cost burn-in test process. Our recent stress tests of analog/mixed-signal CMOS ICs for gate-oxide reliability enhance. This paper presents a control flow model for analog CMOS circuits and uses it to develop a circuit partition scheme. A practically large analog circuit can be partitioned into many smaller sub-circuits so that the developed stress vector generator and stressability analyzer can conformably handle in term of computational complexity. In addition, a structure-based stress vector generation process is also developed. Stress vectors are generated based on the circuit topological structure without performing circuit simulations. The performance improvement proposed in this study can significantly reduce the computational complexity so that the developed stress test system can handle practically large analog CMOS circuits.

Extreme-voltage screening has been successfully implemented to enhance gate-oxide reliability of digital CMOS ICs. However, the success has not yet been extended to its analog counterparts. As a result, almost all the manufacturers employ the digital circuit screening process for the analog modules in mixed-signal CMOS ICs. Our pervious study had addressed the issues on how to properly stress analog circuits to enhance the gate-oxide reliability of mixed-signal CMOS integrated circuits, and the trade-off between the stress coverage and stress time. This paper presents two algorithms that generate a set of stress vectors for an analog circuit (1) to meet the stress coverage requirement and to result in a minimum stress time; and (2) to meet the stress time requirement and to result in a maximum stress coverage.

This paper presents the first-ever research on high-voltage stress of analog circuits to enhance their oxide reliability and to reduce the manufacturing cost. The emphasis of this paper is placed on how to properly stress analog circuits and the development of efficient algorithms for generating stress vectors that meet the stress coverage requirement within a feasible stress time.

No abstract available.

Fault diagnosability analysis is an approach to enhancing the diagnosability of a circuit. Whereas the design for diagnosability ensures that the test points are properly selected and the generation of diagnostic tests is considerably simplified, diagnosability analysis is used to locate sections of a circuit having poor diagnosability. The information allows estimation of a circuit's diagnosability before the fault diagnosis is attempted. Hence any potential problem can be located early on the design phase, allowing modifications to be introduced to improve the final diagnosability. This paper presents a simple diagnosability analysis process in which the diagnosability of a circuit is measured from a graph that describes the circuit topology and a given set of test points, where no circuit simulation is needed. In addition, a simple algorithm is also presented to select a minimum set of test points and their locations for achieving the desired diagnosability.

Given a binary number N, the simplest way for evaluating its square N/sup 2/ is the use of ROM look-up tables. For example, the squares of 12-bit numbers can be stored in a ROM of (2/sup 12//spl times/24) bits, which takes an area of 3.5 mm/sup 2/ and an access time of 9.96 ns with 0.8 /spl mu/m CMOS process. However, the conventional ROM table approaches are limited only for small bit size applications due to the unmanageable increase of the ROM table size. A novel design of square generator circuit using a folding approach is presented for high speed performance applications. Results show that, with the same process, the proposed square generator circuit takes 12.27 ns to generate the squares of 40 bit numbers with an area of about 2.88 times that of the (2/sup 12//spl times/24) ROM, i.e., 10 mm/sup 2/ a design trade-off between speed and area. A nested structure is also presented to achieve a 103 bit square generator with a delay of 15.82 ns. The bit size can be further increased by adding more levels of the nested structure. The results are promising and thus the proposed approach is well suitable for large bit size and high speed applications.

The inductive fault analysis (IFA) technique has been adopted in the previous study for the development of a defect-oriented testability design methodology for analog/mixed-signal integrated circuits. The design methodology defines a collection of fault types and develops a set of testability design rules which define the parameter bounds, generates the test vectors, and valuates the fault coverage. However, the IFA technique requires a tremendous amount of computational time and thus being limited for small circuits. To reduce the computational complexity for reasonably large analog circuits, this paper presents a hierarchical fault macromodeling. Based on the fault modeling for primitive cells in a cell library, a hierarchical fault macromodeling process is developed for establishing macro library to simplify the testability design process.

Based on possible defects on the layout of a practical non-ideal switch, fault model and test generation of current copiers, basic building block of switched-current circuits, are presented in this study. We consider two types of switches, current switches and voltage switches, which have been commonly used in both switched-current circuits and switched-capacitor circuits, and both catastrophic and non-catastrophic faults of transistors used as switches. The generated test sequence achieve full testability of current copiers. The tester and test process are readily applied for any switched-current circuits.

The product of two numbers A and B can be calculated from A/sup 2/ and B/sup 2/. The simplest way for evaluating the squares is the use of ROM look up tables. However the conventional ROM table approaches are limited only for small bit size applications due to the unmanageable increase of the ROM table size. A novel design of square generator using a folding approach is presented to reduce the ROM table size. Results show that the a ROM of (2/sup 12//spl times/24) can store the squares of 12 bit numbers in 9.96 ns and takes 35 mm/sup 2/, where 0.8 /spl mu/mn CMOS process is assumed. With the folding approach, a square generator of 40 bit numbers can be designed using the same ROM table with additional circuitry. The 40 bit square generator takes 12.27ns in delay and 36.45% in hardware overhead. With a two level nested structure, the same ROM table can be used to design a 103 bit square generator which takes 14.58 ns in delay and 3.11 times the area of (2/sup 12//spl times/24) ROM, i.e., 10.9 mm/sup 2/. The bit size can be increased with more levels of the nested structure. The results are promising and thus the proposed approach is well suitable for large bit size applications.

This paper presents the built-in self-test (BIST) design of a C-testable high-speed carry-free divider which can be fully tested by 72 test patterns irrespective of the divider size. Using a graph labeling scheme, the test patterns, expected outputs, and control signals can be represented by sets of labels and generated by a simple circuitry. As a result, test patterns can be easily generated inside chips, responses to test patterns need not to be stored, and use of expensive test equipment is not necessary. Results show that the hardware cost for generating such labels is virtually constant irrespective of the circuit size. For the BIST design of a 64 b C-testable divider, its hardware overhead is less than 5%.

The complexity of quotient-digit selection process can be reduced significantly by using a look-up table, referred to as quotient-digit selection table (QST). However, the huge table size limits such approach for small-radix implementation. This paper presents an alternative quotient decision process to reduce the table size. Instead of finding the exact quotient digit, a speculated quotient digit is estimated. The speculated quotient digit is used to update the possible partial remainders while the speculated quotient digit is corrected. The process includes two steps: determination of speculated quotient digit and quotient-digit correction. Thus instead of using a huge QST table, two smaller tables are employed. Result shows that the proposed approach significantly reduces the size of the original QST.

This paper presents a self-timed converter circuit which converts an n-digit redundant binary number to an (n+1)-bit binary number. Self-timed refers to the fact that the conversion is problem-dependent and requires variable conversion time to complete the operation. The propagation delay of the proposed converter circuit does not increase with the number of digits to be converted, but it is determined by the maximum number of consecutive 0's in that number. This study shows that the statistical upper bound of the average maximum number of consecutive 0's is log/sub 3/n, or 3.78 for 64-digits. This implies that the proposed self-time circuit can be approximately 17 times faster than the ripple-type converter. Thus the proposed converter is well-suited to high-speed, long-word digital arithmetic processors.

This paper presents a built-in self-test (BIST) design of a high-speed C-testable divider. The divider can be fully tested using 72 test patterns irrespective of the circuit size (C-testability). Its test patterns, expected outputs, and control signals can be represented by sets of labels using a graph labeling technique. Due to the simplicity of the repetitive label sets, test patterns can be easily generated inside chips and responses to test patterns need not to be stored. Thus, use of expensive test equipment is not necessary. Results show that, for the BIST design of a 64-bit C-testable divider, its hardware overhead is less than 5%.

Achieving race-free state assignments is an important objective in the synthesis of asynchronous sequential logic circuits (ASLCs). Traditionally, adjacency diagrams are used to help identify and resolve race conditions; however, this approach has a high degree of computational complexity. This paper presents an efficient state assignment algorithm that utilizes a pattern matching technique to predict races and to eliminate the need for enumerative searches. More specifically, the race-free state assignment problem is formulated as the embedding of a bipartite connected graph onto an n-cube and achieves a near minimum number of state variables. This algorithm has been evaluated using several representative examples. Results show that the developed algorithm provides better performance than existing algorithms. Due to the simplicity of the bipartite representation of an n-cube, the developed algorithm is suitable for ASLC synthesis that may involve a relatively large number of states.>

Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques has been employed in analog-to-digital (A/D) converters to eliminate errors caused by offset and low frequency noise and cancel the error effect. For real-time applications, however, it is rather difficult to achieve validation of the converted data in the presence of faulty switching element(s). In this paper, fault behaviors and test generation of a current-mode A/D converter are addressed. Results show that the converter achieves full testability with two test currents. In addition, an A/D converter with concurrent error detection capability is proposed. The converter detects all transient faults.>

Rapid advancements in technology demand innovative computation algorithms and hardware structures to achieve high performance. High speed dividers are commonly designed using SRT division methods. Recently, a high speed carry-free divider design using redundant binary representation has been presented. Based on the carry-free division algorithm and a more general cell fault mode instead of stuck-at fault model, this paper presents a concurrent error detection scheme using alternating input data. The key to the detection of faults is determining that at least one input combination exists for which the error does not result in alternating outputs. Results show that, with a low hardware overhead, the divider circuit is capable of detecting single/multiple transient faults in one cell during the real-time operation and enhancing its reliability significantly.>

Asynchronous sequential logic circuits (ASLCs) are synthesized with either the Huffman model, referred to as HMASLCs, or with the signal transition graph (STG), referred to as STGASLCs. Based on a single stuck-at fault model, this paper describes fault effects for both HMASLCs and STGASLCs and addresses the similarities and differences between them. The fault effects include redundant faults and state oscillations. Input/output redundancy is a special feature of STGASLCs which relaxes the fundamental mode in HMASLCs. Results of this study show that the faults due to the input/output concurrency cannot be tested without a scan structure. This paper presents a scan design technique. ASLCScan. With this structure, the test generation problem is reduced to one of just testing the combinational logic.>

Concurrent error detection (CED) schemes utilizing time redundancy can keep chip area and interconnect to a minimum. An efficient time redundancy scheme, RESO, for array dividers has been reported. Under the same cell fault model, an alternated time redundancy CED scheme using an alternating logic (AL) approach is proposed. The key to the detection of faults using the AL approach is determining that at least one input combination exists for which the error does not result in alternating outputs. Results of this study show that the proposed design achieves the same CED capability as RESO implementation yet with a lower area overhead. Due to the simplicity and low area overhead the proposed AL approach will be very attractive for the design of fault-tolerant VLSI-based systems.>

The yield of ICs has always been crucial to the commercial success of their manufacture. One solution to the low yield problem is to improve the manufacturing and testing processes. This is very costly and quite difficult to implement. The practical approach is to use a fault-tolerant design. In this paper, a design of repairable and fully diagnosable folded PLA is presented, in which the defects can be repaired with-out reconfiguring the external routing. The design achieves a full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults, and has led to a significant yield improvement. The physical layout and floor plan are also provided to assess the chip area.

The yield of ICs is crucial to the commercial success of their manufacture. One practical solution to the low yield problem is the use of fault-tolerant design. A fault diagnosable and repairable PLA design has been proposed to detect, locate, and repair faults, and has led to a significant yield improvement. An alternated defect-tolerant design of PLAs with folding technique is presented to further improve chip yield. The proposed design achieves full diagnosability of stuck-at, bridging, and crosspoint faults during the manufacturing process, and provides full testability after the chip is packaged.>

When a multiple-output function is realized by a PLA (programmable logic array), there is often the option of realizing either true or complementary logic for each output. The tradeoffs in implementing PLAs with and without output phase assignment are explored, and an efficient output phase assignment for PLA minimization is presented. The results of this study show that the proposed algorithm reduces the number of product terms by as much as 50% when the output phase assignment is considered.>

When a multiple-output function (z/sub 1/, z/sub 2/, . . ., z/sub m/) of multilevel logic is realized by complex gates, the option often exists to realize either z/sub i/ or its complement for each output. An efficient output phase assignment for the multilevel logic minimization (OPAM) is presented. The results of this study show that the proposed algorithm further reduces the literal count of the optimized network obtained by MIS (a multilevel logic minimization system).>

In order to ensure the manufacture of large PLA (programmable logic array) chips with reasonable yield level, a design for repairable PLAs (RPLAs) was proposed in which the partially defective chips can be repaired without reconfiguring the external routing. However, before a defective chip can be repaired, the locations of the defects must be precisely identified. The author presents a fault location (diagnosis) scheme that achieves a full diagnosability in locating all single and multiple stuck-at, bridging, and crosspoint faults. Two examples are given to demonstrate the proposed scheme.>

The design of C-testable array dividers that are tested with a test set of constant length irrespective of the circuit size is presented. The results show that the proposed designs of n-by-n nonrestoring and restoring array dividers are C-testable and can be fully tested using only 20 and 40 test patterns, respectively. Algorithms that generate the test patterns and expected outputs are also provided.>

The characteristics of a systolic array and the important issues in fault-tolerant systolic computing are presented. Recent efforts to optimize the performance of a band matrix multiplication systolic array (BMMSA) is discussed, concentrating on the fundamental differences between the Kung-Leiserson and Huang-Abraham schemes of systolic design in order to exemplify the extremes in design philosophies. The motivations for additional figures of merit are pointed out, and a novel BMMSA design is introduced. An efficient scheme, based on the time-redundancy technique of RESO (recomputation with shifted operands), is applied to the design of CED-capable BMMSAs. Different designs, based on the Kung-Leiserson BMMSA, the proposed BMMSA, and the Huang-Abraham BMMSA, are presented.>

Redundancy techniques have been applied to conventional programmable logic arrays (PLAs) to allow for the repair of defective chips. When the redundancy technique is implemented in a VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area, and the additional spare lines can increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair defective chip; then the additional spare lines may increase rather than decrease the chip yields. The possibility of yield enhancement through redundant design is analyzed, showing that the chip yield is increased significantly.>

This paper presents the design of a programmable logic array with redundancy. The design allows for the repair of a defective chip by including the redundancy circuits to a conventional PLA.

In this paper, a new approach to digital testing is presented. This is based on a dynamical modelling technique for the system under test (SUT). The proposed technique consists of an iterative self-test approach, that has been proved to be applicable to analogue fault analysis. A Discrete Component Connection Model (DCCM) is presented as a basis of modelling analysis. The DCCM describes a digital system by using a large-scale dynamic model for a reduction in computation. In this model, difference connection and component equations are simultaneously solved. Fault identification is accomplished by generating a pseudo-system partition of the SUT; a decision process is then executed to validate test results. The decision process is based on a novel Boolean technique for verification of results using a fault bound. This approach is applicable to testing of both sequential and combinatorial logic. Complexity of this testing technique is analysed; a reduction of complexity is accomplished by using covering set theory. Algorithms are presented for both the self-test and the decision processes. The benefits of this approach are computational compatibility to existing complex simulation packages and lower order of complexity of the decision process for single and multiple fault detection and location. Illustrative examples are presented.

This paper describes a set of novel conditions that can be integrated in a computer-aided-testing (CAT) package for repair of redundant RAM's. A new approach is proposed; the innovative feature of this approach is the independence of analysis on the distribution of faulty bits in memory. This results in better exploitation of redundancy and efficient adaptability of this technique to various testing methods, such as the ones that employ region totalizers and fault counters. Algorithms that provide repair solution and earliest detection of unrepairability of a device are presented. The benefits that result by using this approach include a reduction in repair time. Conditions of unrepairability are given as a function of the number of spare resources (columns and rows) in the redundant memory; significant improvement over existing techniques is accomplished. Simulation results are provided to substantiate the validity of the proposed theory.