The Monte-Carlo method is the method of choice for accurate yield estimation. Standard Monte-Carlo methods suffer from a huge computational burden even though they are very accurate. Recently a Monte-Carlo method was proposed for the parametric yield estimation of digital integrated circuits ,that achieves significant computational savings at no loss of accuracy by focusing on those statistical variables that have a significant impact on yield. We adapt this technique to the context of analog circuit yield estimation. The inputs to the proposed method are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The technique operated on digital integrated circuits estimates yield using a linear model for process variations. In our work we first convexify the non-linear design constraints to obtain a convex feasible region. We then consider an accurate polytope-approximation of the convex feasible region by taking tangent hyperplanes at various points on the surface of the convex region. The hyper planes give rise to a matrix of sensitivities, which is then used to glean information about the importance of variables for yield estimation. Finally the knowledge of which design variables are very important for yield estimation is used to allow the Monte-Carlo technique achieve a lower error compared to standard Monte-Carlo in the same amount of simulation time.

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vddvariations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Across-the-chip variability continues to be accommodated by EinsTimer's "Linear Combination of Delay (LCD)" mode. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results.

A (k, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions.

In this paper we concern ourselves with the problem of minimizing leakage power in CMOS circuits consisting of AOI (and-or-invert) gates as they operate in stand-by mode or an idle mode waiting for other circuits to complete their operation. It is known that leakage power due to sub-threshold leakage current in transistors in the OFF state is dependent on the input vector applied. Therefore, we try to compute an input vector that can be applied to the circuit in stand-by mode so that the power loss due to sub-threshold leakage current is the minimum possible. We employ a integer linear programming (ILP) approach to solve the problem of minimizing leakage by first obtaining a good lower bound (estimate) on the minimum leakage power and then rounding the solution to actually obtain an input vector that causes low leakage. The chief advantage of this technique as opposed to others in the literature is that it invariably provides us with a good idea about the quality of the input vector found.