The authors discuss the problem of mapping algorithms for real-time processing of digital video signals onto a fixed configuration of identical programmable video signal processors. Due to the periodic nature of the algorithms and the small periods that are involved, successive executions of the algorithm have to be interleaved in time. The resulting scheduling problem is mathematically modeled and examined. The authors present a novel solution approach that is based on a divide-and-conquer strategy using phase assignment as the central part. This approach has been implemented and it gives good results for industrially significant video applications. Specifically, the proposed approach has been implemented in only 1300 lines of C and has been applied to a number of problem instances, whose signal flow graphs originate from industrially relevant algorithms, including contour enhancement and progressive scan, noise reduction, 4:3 to 16:9 screen format conversion, and a very elaborate progressive scan algorithm.>

The architecture and programming aspects of a programmable video signal processor are discussed.The processor is an integrated circuit that has a modular architecture with a number of programmable, pipelined processing elements.Networks of these processors can be programmed conveniently with the aid of dedicated programming tools.In this paper the emphasis is on the scheduling of video algorithms and the micro code generation for a network of video signal processors.Due to the periodic nature of the video algorithms and the small periods that are involved, successive executions of the video algorithm have to be interleaved in time.We present a novel solution approach to the scheduling problem using phase assignment as the central part.Results of this approach are presented for industrially significant video applications.