PLA adders are described that add in one cycle and require a reasonable number of product terms for an 8, 16, or even a 32-bit adder. A procedure is also described for minimizing the number of product terms for any size adder.

A common requirement accompanying high-speed parallel addition is the early detection that the sum is equal to zero. Normally, this condition is detected from the sum, generally at least two logic gate levels after the sum.

Parallel decimal arithmetic capability is becoming increasingly attractive with new applications of computers in a multi-programming environment. The direct production of decimal sums offers a significant improvement in addition over methods requiring decimal correction. These techniques are illustrated in the eight-digit adder which appears in the System/360 Model 195.

To conserve manpower and reduce the time needed for designing, assembling, and maintaining new large-scale computers, existing computers have been used to produce design and maintenance data for the new machines automatically. This paper describes some techniques that were devised at the National Bureau of Standards for automatically converting a logical design into detailed wiring plans which specify the actual pin-to-pin connections and other data necessary for assembling, debugging, and maintaining a new machine. Starting from punched-card input transcriptions of the logical design of the new computer, expressed in terms of Boolean algebra, an IBM 704 was programmed to produce 20,000 printed pages of wiring plans, fabrication data, and logical debugging and maintenance manuals.

The PILOT data processor is a high-speed multiple computer system, more than 100 times faster than SEAC. It contains three interconnected computers for rapid processing of data, and also contains multiple input-output channels for rapid transfer of data into and out of the system. All of these units operate concurrently in a coordinated fashion. A summary description is given of the over-all logical plan of the system, including the principal characteristics of the first computer, the second computer, the third computer, the internal controls, and the external controls. The system combines internal processing capabilities that are fast and versatile with external communication capabilities that are exceptionally flexible. This combination permits the internal power of the machine to be exploited readily by the outside world,—either by other automatic devices or by human operators.

article Free Access Share on Formal Procedures for Connecting Terminals with a Minimum Total Wire Length Authors: H. Loberman National Bureau of Standards, Washington, D. C. National Bureau of Standards, Washington, D. C.View Profile , A. Weinberger National Bureau of Standards, Washington, D. C. National Bureau of Standards, Washington, D. C.View Profile Authors Info & Claims Journal of the ACMVolume 4Issue 401 October 1957pp 428–437https://doi.org/10.1145/320893.320896Published:01 October 1957Publication History 50citation555DownloadsMetricsTotal Citations50Total Downloads555Last 12 Months82Last 6 weeks20 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

article Free Access Share on Symbolic Designations for Electrical Connections Authors: A. Weinberger National Bureau of Standards, Washington, D. C. National Bureau of Standards, Washington, D. C.View Profile , H. Loberman National Bureau of Standards, Washington, D. C. National Bureau of Standards, Washington, D. C.View Profile Authors Info & Claims Journal of the ACMVolume 4Issue 401 October 1957pp 420–427https://doi.org/10.1145/320893.320895Published:01 October 1957Publication History 1citation295DownloadsMetricsTotal Citations1Total Downloads295Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

An analysis of the functional representation of the carry digits in the addition process shows that the one-megacycle circuitry of SEAC and DYSEAC can be organized logically to permit the formation of many successive carries simultaneously. The Boolean expression for any carry digit Ck can be expanded so as to be an explicit function of only the input digits of orders k to k-p+1 and of the carry digit Ck-p. Certain factorizations can then be made to simplify these expressions so that all of them fall within the limitations on the gating complexity imposed by the circuitry. A parallel adder utilizing this principle is developed which is capable of adding two 53-bit numbers in one microsecond, with relatively few additional components over those required in a parallel adder of more conventional design.

In the course of developing the system plans for the DYSEAC and the SEAC, certain standard methods and procedures were evolved for producing a large-scale digital computer design. These standard procedures cover, first, the development of system specifications, second, the development of functional plans, and finally the development of wiring plans. The later stages of these procedures are reducible to sequences of simple steps, capable of being systematically formulated in explicit terms. The similarity between these procedures and many of the data-processing procedures commonly being executed by present-day computers suggests that, with further development of these design techniques, the wiring plans for new computer systems might well be produced by existing digital machines.