The resource management (RM) of heterogeneous hardware cores within the large-scale embedded systems have been one of the key implementation and research subjects in last years. In future systems, consisting of growing number of heterogeneous hardware cores, the RM have to be implemented to control the energy drain, exploit maximally the performance potential, and also to improve robustness of the system by bypassing failing components. We present the resource management providing an API for parallel execution of operations on a heterogeneous set of resources. The RM controls the tasks execution and monitors the performance. The information collected by the RM is used to optimize the execution. In this paper, we propose and present the SW implementation of the RM for the MicroBlaze soft-core processor running the Linux OS and accelerated by the heterogeneous array of hardware accelerators.

The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGA-based systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique.

Adaptive filters are widely used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. Traditionally, small embedded systems have employed the least computationally intensive filter adaptive algorithms, such as normalized least mean squares (NLMS). This article shows that FPGA devices are a highly suitable platform for more computationally intensive adaptive algorithms. We present an optimized core which implements GSFAP. GSFAP is an algorithm with far superior adaptation properties than NLMS, and with only slightly higher computational complexity. To further optimize resource requirements we use logarithmic arithmetic, rather than conventional floating point, within the custom core. Our design makes effective use of the pipelined logarithmic addition units, and takes advantage of the very low cost of logarithmic multiplication and division. The resulting GSFAP core can be clocked at more than 80MHz on a one million-gate Xilinx XC2V1000-4 device. The core can be used to implement adaptive filters of orders 20 to 1000 performing echo cancellation on speech signals at a sampling rate exceeding 50kHz. For comparison, we implemented a similar NLMS core and found that although it is slightly smaller than the GSFAP core and allows a higher signal sampling rate for the corresponding filter orders, the GSFAP core has adaptation properties that are much superior to NLMS, and that our core can provide very sophisticated adaptive filtering capabilities for resource-constrained embedded systems.

In 2000 we described a proposal for a logarithmic arithmetic unit, which we suggested would offer a faster, more accurate alternative to floating-point procedures. Would it in fact do so, and could it feasibly be integrated into a microprocessor so that the intended benefits might be realized? Here, we describe the European logarithmic microprocessor, a device designed around that unit, and compare its performance with that of a commercial superscalar pipelined floating-point processor. We conclude that the experiment has been successful, and that for 32-bit work, logarithmic arithmetic may now be the technique of choice.

A high performance RLS lattice filter with evaluation of an unknown order of identified system was implemented as an accelerator PCORE for Xilinx EDK. The accelerator hardware can fully exploit parallelisms in the algorithm and remove load from a microprocessor. The EDK integration allows effective programing and debugging of a hardware accelerated DSP applications. The optimal logarithmic number system implementation of the RLS lattice IP core was used. Additionally, the extension by the order probability evaluation was implemented. Then, the core was wrapped in the System Generator. Finally, the generated EDK PCORE was modified to independent clock operation. Implemented solution makes possible evaluation of the RLS lattice filter of order 256 at 8 kHz input data rate in the best case. At the same time the order probability can be maintained. The implementation outperforms software solution up to 74 times and it is also performing 40% faster than other known solutions.

Adaptive filters are widely used in digital signal processing for such applications as system identification, noise cancellation, and in areas such as digital communication systems. Traditionally, small resource-constrained embedded systems have used the least computationally intensive filter adaptive algorithms based on least mean squares (LMS).The power-normalized version (NLMS) is typical example. More complex adaptive algorithms, such as recursive least squares (RLS), are usually too computationally expensive for implementation in small embedded systems.Our work deals with a floating-point-like implementation of the Gauss-Seidel fast affine projection (GSFAP) algorithm and shows that FPGAs are a highly suitable platform for more computationally intensive adaptive algorithms. FAP based algorithms are characterized by better adaptation properties than NLMS with only a slightly higher complexity, providing some compromise between the slow convergence of NLMS and the computational complexity of RLS.We present the design of an optimized core which implements GSFAP. To reduce the resource requirements we use logarithmic arithmetic, rather than conventional floating point, within the custom core. Our design makes effective use of the pipelined logarithmic addition units, and takes advantage of the very low cost of logarithmic multiplication and division.The resource requirements of the resulting GSFAP core are slightly higher than the requirements for the corresponding NLMS core. However, experiments show that GSFAP has adaptation properties much superior to NLMS which is demonstrated on a noise/echo cancellation example.

Our poster introduces an innovative RLS Lattice filter implementation for FPGAs. The signal processing applications typically require wide numeric range, and that poses a problem when using an FPGA implementation. Our approach is based on arithmetic using logarithmic numeric representation (LNS). The test application - an adaptive noise canceller - has been optimized for the Xilinx Virtex devices. It consumes roughly 70% of all logic resources of the XCV800 device and all block memory cells. The filter orders up to 252 at 7 kHz sampling frequency have been achieved using the 19-bit LNS arithmetic. The maximum performance of the application is about 70 MFLOPs including i/o conversions. It has been shown that the custom filter design can be 10 times faster than commonly used solutions. This work was supported by the Ministry of Education of the Czech Republic under Project No. LN00B06.