Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Makoto Ishida

dblp:47/6837 · DBLP profile ↗
← Back
3ranked-venue papers
0as first author
0since 2021 · last 2011
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design
arithmetic circuit design
0.011994
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits · IEEE Trans. Computers 1994
Integrated circuit design
digital circuit design
0.011994
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits · IEEE Trans. Computers 1994
Integrated circuit design › digital circuit design › arithmetic circuit design
multiplier design
0.011994
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits · IEEE Trans. Computers 1994
Integrated circuit design › digital circuit design
multivalued logic circuit
0.011994
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits · IEEE Trans. Computers 1994

Methods — techniques the papers use, named apart from their topics

redundant number representation · 0.0carry-propagation-free addition · 0.0
YearPublicationVenuePosition
2011 Multimodal proton and fluorescence image sensor for bio applications
abstract
We developed a multimodal sensor for proton (pH, power of Hydrogen) and filter-less fluorescence imaging by using CMOS (complementary metal-oxide semiconductor) silicon integrated circuit technology. In the developed device, a proton sensor which uses CCD (charge-coupled device) image sensor technology and a filter-less fluorescence detection sensor are fused in the same pixel. Both pH and fluorescence images were first ever successfully obtained without optical filters or gratings and simultaneously in the same area in real time using the developed image sensor.
Hirokazu Nakazawa, Makoto Ishida, Kazuaki Sawada
VLSI-SoC2
1996 Author's Reply
Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi 0001
IEEE Trans. Computers2
1994 High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
abstract
Presents a very-large-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as /spl lcub/0,1,2,3/spl rcub/ and /spl lcub/0,1,2,3,4/spl rcub/. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set /spl lcub/0,1,2,3/spl rcub/ in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.>
Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi 0001
IEEE Trans. Computers2