This paper demonstrates a 12-bit 100-MS/s PVT-stabilized pipelined-SAR ADC with fully integrated on-chip calibration. Two key innovations facilitate over 65-dB SNDR with less than 2.2-dB variation from -20 °C to 125 °C: First, a PVT-stabilized nested negative-C topology boosts open-loop gain ($G_{ol}$) of the residue amplifier (RA) by 28 dB, enabling one-time foreground calibration that avoids persistent inter-stage gain error tracking. Second, a dynamic auto-zeroing technique addresses offsets from both the RA and first-stage comparator through a switched-capacitor filter that extracts offsets based on the stochastic characteristics of residue signals. Dynamically level-shifted capacitors (DLSC) are embedded at the differential inputs to neutralize aliased noise and thermal noise, so that the offset drifts under high-temperature environment are effectively cancelled. Fabricated in 40-nm CMOS, the prototype occupies 0.22 mm2and achieves 65.5-dB SNDR and 83-dB SFDR at Nyquist input while consuming 3.7 mW. Across six tested chips, the prototype design exhibits merely 2.2-dB SNDR degradation over -20 °C ~ 125 °C and 1.3-dB variation under ± 5 % supply voltage (1.1 V) fluctuations.

The JESD204C receiver has emerged as a mainstream SerDes interface in high-speed analog-to-digital converters (ADCs). However, it faces challenges such as long link initialization time, substantial hardware area and power consumption. To address these issues, this paper presents an optimized link-layer design for the JESD204C receiver, with a focus on enhancing synchronization header (SH) detection efficiency and reducing the area of Cyclic Redundancy Check (CRC) and Forward Error Correction (FEC) decoding circuits. First, a dynamic search space(DSS)-based SH detection method is proposed. Leveraging multi-level XOR logic, this method efficiently eliminates non-transition bits from the data stream, enabling rapid localization of the 2-bit SH and thus shortening the synchronization delay during link establishment. Second, to mitigate the large area overhead of the data link layers decoding module, a CRC and FEC decoder (CAFD) with a logic-sharing architecture is designed: common factors in the decoding process are identified and shared, significantly reducing redundant hardware resources. Additionally, a low-complexity critical path identification algorithm is introduced to guide factor-sharing constraints, ensuring the decoder meets timing requirements while optimizing area. Finally, the proposed JESD204C receiver is implemented with a 28-nm CMOS process and verified on an FPGA platform. Experimental results show that the design not only eliminates redundant SH detection operations and accelerates link initialization/synchronization but also improves hardware resource utilization. Compared with state-of-the-art solutions, the hardware area and power consumption are reduced by 47.6% and 15.1%, respectively, while the SH locking time is shortened by 60%.

This paper presents a low-noise class-F23voltage-controlled oscillator (VCO) with harmonic resonance expansion and$2^{\mathrm {nd}}$/$3^{\mathrm {rd}}$-harmonic outputs for multiband mm-wave applications. By using a single four-coil transformer to extend the common-mode (CM) and differential-mode (DM) harmonic resonance bandwidths, the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic resonances can be acquired without additional frequency alignment calibration. Meanwhile, benefiting from the favorable differential response at the$2^{\mathrm {nd}}$- and$3^{\mathrm {rd}}$-harmonic frequencies, the corresponding harmonic frequency outputs are extracted, simultaneously. Fabricated in 65-nm CMOS process, the proposed VCO achieves a frequency tuning range (FTR) of 20.8% from 10.71 GHz to 13.20GHz with 1-MHz offset phase noise (PN) from -117.4 to -114.5 dBc/Hz, while consuming 7.8-9.8 mW at 0.6 V. The VCO core area is only 0.054 mm2and the flicker noise corner is 310-450 kHz. The figure-of-merit (FoM) at 10-MHz offset scores 189.8-191.7 dBc/Hz. The harmonic outputs achieve a FTR of 21.42-26.40 GHz and 32.13-39.60 GHz, with a 1-MHz-offset PN from –110.5 to –107.5 dBc/Hz and –107.6 to –104.8 dBc/Hz.

This article presents a 5-GS/s 8-bit single-channel hybrid analog-to-digital converter (ADC) with a$\lambda $/4 transmission line (T-Line) based time-to-digital converter (TDC). Taking advantage of the traveling wave technique, the T-Line based TDC breaks the time step (TLSB) limitation caused by jitter tolerance and process, voltage, and temperature (PVT) variations. An improved bootstrapped generator for the input switch enables rapid start-up and reduces tracking time, accommodating the high sampling rate. Fabricated in a 28-nm CMOS technology, the prototype ADC core consumes 19.8 mW at 5 GS/s with a 0.9-V supply. It achieves a signal-to-noise and distortion ratio (SNDR) of 38.04 dB with a Nyquist input, corresponding to a Walden figure-of-merit of 60.7 fJ/conv-step. The measured variation in SNDR is below 0.34 dB across temperature variation of$- 25~^{\circ }$C to$125~^{\circ }$C, and below 0.74 dB over supply variations of ±5%.

This paper presents a fully integrated reconfigurable single-channel IC with high energy efficiency for bio-signal acquisition in Internet-of-Medical Things (IoMT) systems. The overall signal chain consists of a capacitively-coupled instrumentation amplifier (CCIA) and a 16-bit delta-sigma ($\Delta$$\Sigma$) ADC. The ADC is directly driven by the CCIA without a traditional driver stage. The folded path of the first stage in CCIA is sliced for reconfigurable noise levels. In addition, a single-stage floating inverter amplifier (FIA) assisted by the correlated-level-shifting (CLS) technique is employed in the switched-capacitor (SC)$\Delta$$\Sigma$modulator for fully dynamic operation with sufficient DC gain. Fabricated in 180-nm CMOS, the CCIA achieves an input-referred noise level ranging from 35.8 to 67 nV/$\surd$Hz with a best noise-efficiency factor (NEF) of 5.54. It corresponds to an integrated noise ranging from 0.63 to 1.16$\mu$$\text{V}_\text{rms}$(0.5-100 Hz) and 1.93 to 3.51$\mu$$\text{V}_\text{rms}$(0.1-3 kHz), respectively. The ADC achieves a peak SNDR of 92.6 dB for a 2.3-$\text{V}_\text{pp}$differential input and can support 16$\times$power/BW reconfigurability with ENOB$>$15 bit. The complete system occupies an active area of 0.56 mm$^{2}$and achieves 85.7-dB system SNDR over a 500 Hz BW with an OSR of 128. It consumes 36.8$\mu$W from a 1.8-V supply, corresponding to an SNDR-based Schreier FoM of 157 dB. Biological measurement is demonstrated successfully, and the results verify that the proposed IC is applicable to high-quality ExG signal acquisition.

In this paper, we present an ultra-low power wake-up receiver (WuRX) with effective interference suppression capability. A specific robust design has been implemented to address the common interference issues in the industrial, scientific, and medical (ISM) frequency band. A mathematical expression is derived in this paper for the minimum signal-to-noise ratio (SNR) required by the comparator at which a envelope detector first (ED-first) WuRX can detect the wake-up message in the presence of interference. Aiming to meet the minimum SNR requirements, a quasi-direct coupling (QDC) baseband buffer scheme is proposed. Compared to the output SNR of traditional AC schemes, the QDC baseband buffer scheme achieves a 4.16 dB increase in output SNR under optimal conditions. To solve the problem where traditional comparator calibration schemes require recovery time after sudden disappearance of interference, the multipath signal detection (MPSD) scheme proposed in this paper can immediately detect information following the disappearance of interference, which improves detection efficiency. The WuRX is manufactured in 65nm LP process, consuming 7.56nW at a 0.4V power supply, with a sensitivity of −79dBm in the 433MHz ISM band. Under continuous wave (CW) interference, the receiver achieves a signal-to-interference ratio (SIR) of −31dB at a frequency offset of 1MHz.

This brief proposes a 7.4–9.2-GHz low-noise fractional-N differential sampling phase-locked loop (DSPLL), which features doubled phase detector (PD) gain. By using the phase-domain and voltage-domain hybrid calibration, the accumulated quantization error (Q-error) of the delta-sigma modulator (DSM) is compensated, and the locking problem caused by large sampling voltage fluctuation is solved. Meanwhile, a voltage shifting technique is introduced to adjust the locked voltage region of differential sampling PD (DSPD), which can improve the linearity of DSPLL for better calibration. Fabricated in 65-nm CMOS process, the presented DSPLL achieves measured integrated jitter of 69.09 and 73.26 fs for integer-N and fractional-N modes, respectively. The reference spur is −72.96 dBc, and the worst fractional spur is −55.26 dBc. The total power consumption is 19.2 mW at a 1.2-V supply, achieving a figure of merit jitter (FOMJ) of −249.9 dB.

A digital background calibration technique is proposed in this brief, utilizing comparator metastability to correct conversion errors from interstage gain errors and higher order nonlinearities for the first time. The method calibrates nonlinear conversion errors by injecting multilevel dithers and observing amplifier gain variations. It offers advantages, such as simple design, high accuracy, fast convergence, and low power consumption. Simulation results demonstrate the effectiveness of the technique, with the signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) performances of a 14-bit two-stage pipelined successive approximation register analog-to-digital converter (SAR ADC) improving from 60.4 and 73.6 to 84.5 and 110.0 dB, respectively. The convergence speed of the calibration algorithm is 0.8 million samples.

This brief presents an on-chip, real-time rotation calibration (RRC) technique aimed at alleviating the inter-channel offset mismatch in time-interleaved (TI) successive-approximation register analog-to-digital converter (SAR ADC). By leveraging auto-rotation calibration and self-compensation strategies in the analog domain, the proposed technique demonstrates robust performance across PVT variations. Two additional sub-channels are involved in the TI quantization mechanism, where the continuous rotation of the sampling clock distribution ensures their operation in calibration mode. To validate the effectiveness of the proposed calibration, an$8\times 8$bit 8 GS/s TI-SAR ADC is designed and implemented in a 28-nm process and occupies an active area of 0.273 mm2, with each sub-channel SAR ADC covering only$86\times 23~\mu $m. Extensive simulation results validate the efficacy of RRC, demonstrating significant improvements in dynamic performance. Specifically, SNDR increases from 37.1 to 45.4 dB, while SFDR rises from 57.8 to 60.7 dB, as observed at the Nyquist input frequency.

This paper presents an integer-N sampling phase-locked loop (S-PLL) characterized by both low jitter and low spur. The design integrates a high-gain double-edge sampling phase detector (PD) and a self-retimed multi-modulus divider (MMD) aimed at mitigating the in-band noise. Furthermore, it features a compact implicit common-mode voltage-controlled oscillator (VCO) with a second harmonic tuning tailored for noise reduction. The proposed S-PLL, fabricated in a 28-nm CMOS technology, operates at 31 GHz with a 250-MHz reference. The measured RMS jitter is 39.69 fs integrated from 10 kHz to 100 MHz, with a reference spur of −63.2 dBc. The proposed PLL achieves a figure-of-merit (FoM) of −253.6 dB with a 28-mW power and a 0.047-mm2area.

Linearity testing, including differential nonlinearity (DNL) and integral nonlinearity (INL), is of great significance to evaluate the performance of an analog-to-digital converter (ADC). However, highly linear signal generator and large amount of samples are two challenges in conventional histogram testing method. This paper proposes a segmentation nonlinear model with partial polynomial fitting to reduce the required samples, while the source nonlinearity removal scheme relaxes the precision requirement of signal generator. The influence of noise and source resolution are analyzed. Measurement results show that with a 12-bit digital-to-analog converter (DAC) and 393 216 samples, the 16-bit ADC INL and DNL can be measured with estimation errors less than 0.3 LSB.

This paper presents a digital background timing-skew calibration technique with high accuracy and bandwidth in time-interleaved (TI) analog-to-digital converters (ADCs). Compared with other calibration works, it features three highlights. Firstly, the proposed DCSD-based step-by-step and grouping calibration scheme can effectively improve the correction accuracy by minimizing the root mean square (RMS) value of the detected timing skews. Secondly, the linear compensation for a 13-taps FIR filter and the decimation-calibration-interpolation working pattern are used to expand the calibration effective bandwidth to the whole first Nyquist zone from different perspectives. Thirdly, the binary search is employed, instead of LMS algorithm, in order to meet the compensation requirement for FIR filter and improve the convergence speed and accuracy significantly in timing-skew detection. As a result, the proposed technique achieves the widest calibration bandwidth and higher accuracy compared to other fully digital calibration techniques while having the great convergence speed. Simulation model in MATLAB and FPGA-based hardware verification are employed to demonstrate its significant improvement on the performance and hardware overhead of the TI-ADCs. Finally, the proposed technique is employed in a 10-bit 2.5 GS/s 4-way TI-SAR ADC fabricated by standard CMOS 28nm process. The measurement results show that with the proposed technique, the SFDR and SNDR are improved by 18.9 and 17.9 dB at Nyquist frequency, respectively.

This paper introduces a dual main clock generator (DMCG) and a digital serializer (DS) to improve the power efficiency of the time-interleaving (TI) analog-to-digital converters (ADCs). The proposed DMCG combines a dual-path front end and an improved selecting signal generator that addresses the potential phase error and reduces the peak current of the clock-driving circuits by 60%. The DS is proposed to serialize the digital outputs without employing power-hungry inverter-based buffer chains thus reducing the power consumption by 39.2%. The reference-free time skew extraction algorithm (RFA) is presented to mitigate the accuracy deterioration due to selecting the fixed middle channel. These techniques are validated by a prototype 12-bit 10-GS/s TI pipelined successive approximation register (TI-Pi-SAR) ADC. Fabricated in a 28-nm CMOS process, the prototype chip occupies an area of 4.4 mm2. The measurement results show that the ADC achieves a 49.8 dB SNDR and 60.0 dB SFDR after calibration at Nyquist frequency, while the total power consumption is 270 mW, leading to the figure of merits of Schreier (FoM$_{\mathrm {S}}$) and Walden (FoM$_{\mathrm {W}}$) of 152.5 dB and 106.9 fJ/conv.-step, respectively.

This article presents a fully dynamic switched-capacitor zoom ADC with 1st-order interstage leakage shaping (ILS). Noise shaping capability is integrated into the coarse stage by a low-cost error-feedback (EF) path, effectively mitigating quantization noise leakage in the traditional zoom architecture due to the non-unity STF. In addition, a swing-enhanced floating inverter amplifier (FIA) architecture is proposed for improved linearity as well as fully dynamic operations. The prototype ADC is fabricated in a 65-nm CMOS process and occupies an active area of 0.22 mm2. With a 1.2-V supply, it achieves 98.1-dB peak SNDR over a 20-kHz bandwidth with 142.8$\mu $W power consumption, resulting in a DR-based Schreier FoM of 182.9 dB and an SNDR-based FoM of 179.5 dB, respectively. According to the measurement results, 8$\times $power/BW configurability can be achieved by the zoom ADC while maintaining SNDR above 98 dB.

This paper presents a$G_{m}$-C integrator-implanted DC servo loop (GMCI2-DSL) and a bulk-driven ripple reduction loop (BD-RRL) for bio-potential readout analog-front-end (AFE) amplifier. The proposed bio-potential readout AFE amplifier employs the GMCI2-DSL and BD-RRL to achieve low noise and significant total harmonic distortion (THD) with small ripple amplitude. A prototype has been taped out using a 0.18-$\mu \text{m}$standard CMOS technology, and the core circuit occupies 880$\mu \text{m}\,\,\times $630$\mu \text{m}$. The mid-band gain is about 40 dB with a 1.3-V supply voltage, and the chip’s quiescent power is 10.8$\mu \text{W}$. The measured results show that the input-referred noise density is 26 nV/$\surd $Hz, and the input-referred integrated noise in the range from 0.5 Hz to 500 Hz is 0.93$\mu V_{rms}$. The measured THD of a 5-$\text{m}V_{pp}$input sinusoidal signal at 5.1 Hz is −64.3 dB without any input offset. The amplitude of residue ripple is achieved as 197.8$\mu \text{V}$around chopping frequency ($f_{ch}$) by ripple suppression. High-fidelity and real-time electrocardiogram (ECG) signals are acquired.

A highly linear input buffer is crucial for high-speed and high-resolution analog-to-digital converters (ADCs) since it isolates the kickback noise and package inductance. Several important factors affecting the linearity of the input buffer are analyzed in this brief, and a wideband input buffer with high linearity based on cascade complementary source follower (CCSF) is proposed. This cascaded input buffer is composed of a pMOS source follower (PSF) and an nMOS source follower (NSF). Compensation capacitor, assisted operational amplifier (opamp), bootstrapped-capacitor level-shifting circuit, current amplifier, and optimization strategies are utilized to extend the bandwidth and reduce distortion. Designed in a 65-nm CMOS, the CCSF input buffer achieves the spurious-free dynamic range (SFDR) and a signal-to-noise and distortion ratio (SNDR) of 76.6 and 58.1 dB with 1.9-GHz input frequency, respectively. It occupies 0.0155 mm$^2$and consumes 27 mW at 2.5 V.

This article presents a high-speed time-domain (TD) 4-bit/cycle successive approximation register (SAR) analog-to-digital converter (ADC). After converting the voltage input to the time domain, the compact interpolation-based time-to-digital converter (TDC) resolves 4-bit in each SAR cycle with$16\times $linear TD interpolation. This scaling-friendly architecture reduces the number of capacitive digital-to-analog converters (CDACs) and voltage-to-time converters (VTCs) significantly, leading to low power, small area, low kickback noise, and small input loading. A cascade current-starved inverter based VTC is used in the second SAR conversion cycle, which improves voltage-to-time gain and ensures speed and linearity. Besides, to reduce the TD interpolation error and eliminate the short-circuit current, a novel phase interpolator is proposed. A two-way time-interleaved 7-bit 3.8-GS/s prototype ADC was fabricated in a 28-nm CMOS, occupying an active area of 0.01 mm2. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.9 and 50.8 dB, respectively. Consuming 7.5 mW at 1.0 V supply, the Walden figure of merit (FoMw) is 24.4 fJ/conversion-step.

This paper presents a coarse-fine bypass window technique to improve the energy efficiency of the successive approximation register (SAR) analog-to-digital converter (ADC) by skipping unnecessary conversion cycles when the input signal is within the bypass windows. It utilizes the time information of the MSB comparison to coarsely detect the input range without a dedicated timing budget. Based on the coarse detection results, the fine bypass window is configured by reusing the digital-to-analog converter (DAC) to accurately detect the input signal. Due to the presence of the coarse detection, the multi-window detection and its corresponding bypass operation are realized to maximize the effectiveness of the bypass window technique. In addition, the MSB-spilt switching scheme is proposed to reduce the DAC switch-back energy. A prototype 8-bit SAR ADC equipped with the proposed technique is fabricated in a 65-nm CMOS process. At a 350-MS/s sampling rate with a Nyquist input, the measured signal-to-noise-plus-distortion ratio (SNDR) and spurious-free dynamic ranges (SFDR) are 44.9 dB and 63.9 dB, respectively. At a supply voltage of 1.2 V, the ADC consumes power of 1.58 mW with the full-scale sinusoidal input signal. The ADC achieves an effective number of bits (ENOB) of 7.17 bit, resulting in a figure-of-merit (FoM) of 31.3 fJ/conversion-step. The ADC core occupies an active area of 0.0096 mm2.

This article presents a single-loop third-order discrete-time delta-sigma modulator (DTDSM) with a 4-bit second-order noise shaping successive approximation register (NS SAR) quantizer. To realize an aggressive noise transfer function (NTF), a novel Finite Impulse Response (FIR) filter is embedded in the NS SAR. As employing a flipped voltage follower (FVF), which offers unity gain instead of an open loop dynamic amplifier, the proposed FIR filter is sharp and insensitive to process, voltage, and temperature (PVT) variation. Fabricated in a 65-nm 1P9M CMOS technology, the prototype DTDSM consumes$44 \mu \text{W}$when operating at a 1.2-V supply voltage and a sampling rate of 2.4 MS/s. It achieves a peak Schreier figure of merit (FoM) of 177.9 dB with a signal-to-noise and distortion-ratio (SNDR) of 91.3 dB at an oversampling ratio (OSR) of 64.

This article presents a constant voltage control scheme to improve the transfer efficiency and output voltage accuracy for single-stage AC-DC converters. The proposed scheme also has the advantage of low cost because of the simple application and few peripheral devices. To realize above features, the peak current and frequency curves with high efficiency are selected by analyzing the power losses of the applied topology. A voltage self-compensation circuit is designed to improve the output accuracy, especially the output voltage below 5V. Furthermore, a multi-stage startup circuit is also proposed to reduce the output voltage overshoot. To verify the feasibility of the proposed constant voltage control scheme, a BUCK controller adopting the proposed control scheme has been designed and fabricated with$0.18~\mu \text{m}$BCD process. Using the proposed controller, the peak efficiency of the prototype can reach as high as 66.9%, 78.9% and 82.8% under 115Vac input and 3.3V@300mA, 5V@300mA and 12V@300mA respectively. The load regulation is counted to be within ±1%.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, voltage control readout technique suffers from poor noise performance and low power efficiency (in terms of FoM). In this paper, the weak feedback oversampling successive approximation readout circuit which merges the closed-loop hybrid dynamic amplifier with noise reduction technique is proposed to achieve low noise floor, high power efficiency and high accuracy. The proposed WFB-OSA based readout circuit is fabricated in a commercial$0.18\mu \text{m}$1.8V CMOS process. The measurement result shows that the circuit has achieved a noise floor of$63\mu g/\surd Hz$and an FoM of 14pJ.

This brief presents an 8-bit two-step successive approximation register analog-to-digital converter (SAR ADC), where the interstage gain is embedded in the second-stage comparison to eliminate the dedicated residue amplifier and its timing cost. Combined with the passive residue transfer technique, the prototype ADC realizes high speed while requiring small overhead. Fabricated in 28-nm CMOS, it operates at 1.5 GS/s and achieves an signal-to-noise-and-distortion-ratio (SNDR) of 43.3 dB at Nyquist rate while consuming 2.32 mW, resulting in a Walden figure-of-merit (FOM) of 12.9 fJ/conv-step.

This brief presents a single-channel 8-bit 1.5-GS/s voltage–time (V-T) hybrid two-step analog-to-digital converter (ADC). Benefiting from the fine quantification in the time domain, the power-to-noise requirement of a comparator and speed limitation in the voltage domain have been significantly relaxed. An efficient cross-coupled linearized technique (CCLT) is proposed in a dynamic voltage-to-time converter (VTC) design as a crucial part of this ADC. This technique helps improve the total harmonic distortion (THD) of VTC by 8 dB across most process–voltage–temperature (PVT) variations by avoiding using a power-harvest current-source (CS)-based VTC. Moreover, a dynamic conversion strategy is proposed in a time quantizer to build a more power-efficient design. Fabricated in a 28-nm CMOS process, the prototype ADC consumes 3.3 mW at 1-V supply with an active area of 0.0035 mm2. With a Nyquist input, it achieves a signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 45.4 and 60.3 dB, respectively, yielding a Walden figure of merit (FoMW) of 14.4 fJ/conversion-step.

In this paper, a single-channel two-step voltage-time hybrid domain analog-to-digital converter (ADC) is proposed. To achieve high sampling rate and high accuracy, 3.5-bit voltage domain MDAC and 7-bit high-speed time domain ADC (TD-ADC) are combined into a 10-bit hybrid ADC. In the first stage MDAC, a low-power push-pull amplifier is used to improve settling speed, and 1-bit redundancy is designed for calibration and dither injection. The TD-ADC with selective time domain quantization is implemented by a constant-current voltage to time converter (VTC) array and a direct positive feedback time domain comparator. The proposed VTC array can maintain high linearity with a large input swing in high-speed application. The prototype ADC was fabricated in a 28-nm CMOS process and occupied a core area of 0.074 mm2. Under a 0.95-V power supply, the chip achieves a measured peak SNDR of 53.2 dB and SFDR of 61.7 dB respectively at conversion rate up to 2.5 GS/s. The FOM is 48.2 fJ/conversion-step.

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW,includingon-chip reference buffers.

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than closed-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, the voltage control readout technique suffers from low dynamic range and low power efficiency (in terms of$\mathbf {FoM}$). In this paper, the voltage control ratiometric (VCR) readout technique is proposed to improve both dynamic range and power efficiency. The VCR readout technique is demonstrated in a readout circuit fabricated in a commercial 0.18$\mu {\mathrm{ m}}$1.8V/5.0V CMOS process. Compared to the traditional voltage readout circuit fabricated with the same CMOS process and tested with the same sensing element, the VCR readout circuit improves full input signal range by$\mathbf {3.5dB}$(from$\boldsymbol {\pm 8g}$to$\boldsymbol {\pm 12g}$) and the noise floor by$\mathbf {9.5dB}$(from$\mathrm {\mathbf {804~\mu g/}}\sqrt {\mathbf {Hz}} $to$\mathbf {270~\mu g/}\sqrt {\mathbf {Hz}} $). As a result, the dynamic range is improved by$\mathbf {13.0dB}$(from$\mathbf {44.0dB}$to$\mathbf {57.0dB}$), the$\mathbf {Fo}\mathbf {M}_{\mathbf {1}}$is improved from$\mathbf {310pJ}$to$\mathrm {\mathbf {83pJ }}$and the$\mathbf {Fo}\mathbf {M}_{\mathbf {2}}$is improved from$\mathbf {1977~\mu W\cdot \mu g/Hz}$to$\mathbf {796~\mu W\cdot \mu g/Hz}$.

A single-channel reconfigurable successive approximation register (SAR) analog-to-digital converter (ADC) is presented, which features its speed expanding with conversion mode. The reconfigurable capacitor digital to analog converter (CDAC) is proposed to achieve multiple conversion modes without wasting capacitance. In 1-b/cycle conversion mode, the proposed ADC can achieve the sampling rate of 60-Ms/s and 9-b resolution. Based on the 2-b/cycle conversion mode, the proposed ADC can double the sampling rate and be reconfigured as a 120-MS/s, 8-b converter. Besides, the detection skip algorithm and charge sharing technology are involved to remove the precharge operation time and reduce the switching energy consumption. Moreover, the control logic is optimized to minimize the chip area and matches the reconfigurable characteristics well. A prototype ADC is fabricated in the 180-nm standard CMOS process, which achieves the 54.1-/46.7-dB signal-to-noise-plus-distortion ratio (SNDR) at 60-/120-MHz sampling frequency with the power consumption of 1.9/3.5 mW. The prototype ADC achieves a peak figure of merit (FoM) of 77-fJ/Conv.step at 2-b/cycle conversion mode. The ADC core occupies an active area of only 0.12 mm2.