Stephen Bique

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2ranked-venue papers

1as first author

0since 2021 · last 2008

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 1Systems, architecture and hardware · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer graphics and multimedia 1 paper		Image and video coding · 100%
Computer architecture, parallel and distributed computing, and storage systems 1 paper		Hardware accelerators and domain-specific architectures · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Image and video coding › transform coding discrete cosine transform	0.1	1	2005	New Characterizations of 2D Discrete Cosine Transform · IEEE Trans. Computers 2005
Image and video coding transform coding	0.1	1	2005	New Characterizations of 2D Discrete Cosine Transform · IEEE Trans. Computers 2005
Hardware accelerators and domain-specific architectures › machine learning accelerator transform accelerators	0.0	1	2005	New Characterizations of 2D Discrete Cosine Transform · IEEE Trans. Computers 2005

Methods — techniques the papers use, named apart from their topics

serial-parallel architecture · 0.1algebraic characterization · 0.1

Year	Publication	Venue	Position
2008	Component Selection to Optimize Distance Function Learning in Complex Scientific Data Sets Aparna S. Varde, Stephen Bique, Elke A. Rundensteiner, David C. Brown, Jianyu Liang, Richard D. Sisson Jr., Ehsan Sheybani, Brian Sayre	DEXA	2
2005	New Characterizations of 2D Discrete Cosine Transform abstract We introduce a function to specify the transform coefficients. We state, prove, and apply useful rules. Our combination of two algorithms is unique. We describe an implementation for an 8/spl times/8 DCT that performs a total of 1,424 operations at a rate of 178 operations per clock cycle, which is approximately twice as fast as a unified algorithm on a serial-parallel architecture. Stephen Bique	IEEE Trans. Computers	1