The growing number of connected devices and emerging 5G use cases demand backhaul solutions that are flexible, scalable, and easy to deploy. While fiber and microwave remain common, their limitations in mobility highlight the need for wireless alternatives. This work compares three approaches based on 5G New Radio (NR): Integrated Access and Backhaul (IAB), emulated IAB, and Wireless Access Backhaul (WAB). After introducing their concepts and architectures, this document presents their implementation in an OpenAirInterface (OAI)-based testbed and evaluates their performance under comparable conditions. The goal is to provide a balanced analysis of these options, outlining their main advantages and limitations to guide the selection of suitable backhaul strategies.

Light detection and ranging (LiDAR) sensors provide accurate 3D vision to a vehicle, thus being fundamental for safe driving. However, currently available LiDARs rely on short pulse waveforms, which are permeable to interference. As more LiDAR sensors are deployed, interference between LiDARs shall be aggravated, jeopardizing reliable 3D vision and thus safe driving.In this paper, we propose a waveform that is robust against interfering pulses, while sacrificing as little range as possible. The proposed waveform consists of two pulses of known relative amplitude and position. A matching estimation method comprising a simple validation stage followed by a LightGBM-based estimation stage is presented. Such a method is demonstrated using an experimentally acquired dataset comprising interference-free signals as well as signals impaired by one interfering pulse.Over 97% of all interference-riddled signals are validated, and result in accurate estimations. In fact, estimations from interference-free signals are as accurate as estimations from a single pulse with the same average power, showing that resilience against interfering pulses was obtained without sacrificing estimation performance.

This article presents the deployment and experimentation architecture of the Aveiro Tech City Living Lab (ATCLL) in Aveiro, Portugal. This platform comprises a large number of Internet of Things (IoT) devices with communication, sensing, and computing capabilities. The communication infrastructure, built on fiber and millimeter-wave (mmWave) links, integrates a communication network with radio terminals [WiFi, ITS-G5, cellular vehicular-to-everything, 5G and LoRa(WAN)], multiprotocol, spread throughout 44 connected points of access in the city. Additionally, public transportation has also been equipped with communication and sensing units. All these points combine and interconnect a set of sensors, such as mobility (radars, light detection and rangings (LiDARs), and video cameras) and environmental sensors. Combining edge computing and cloud management to deploy the services and manage the platform, and a data platform to gather and process the data, the living lab supports a wide range of services and applications: IoT, intelligent transport systems (ITSs) and assisted driving, environmental monitoring, emergency and safety, and among others. This article describes the architecture, implementation, and deployment to make the overall platform to work and integrate researchers and citizens. Moreover, it showcases some examples of the performance metrics achieved in the city infrastructure, the data that can be collected, visualized, and used to build services and applications to the cities, and, finally, different use cases in the mobility and safety scenarios.

In this paper, we present a low-resource look-up table (LUT) based solution for all-digital transmitters (ADTs) that addresses both the wide bandwidth and high carrier frequency flexibility. Traditional ADTs use real-time delta-sigma modulation (DSM) to convert a multiple-bit signal into a single-bit one, enabling the use of fast and inexpensive one-bit digital-to-analog converters (DACs) in the transmission chain. However, real-time DSM requires significant computational power to provide wide bandwidths and high carrier frequency agility. Our LUT-based solution achieves carrier frequency agility from 0.1 GHz to 7.62 GHz and delivers wide bandwidths of up to 150 MHz. We also introduce a new technique called “Half LUT Implementation” that allows us to halve the size of the LUT without sacrificing performance. The focus on simplifying and reducing resources in the transmitter is intended to reduce energy consumption and enable ADTs to be used in massive multiple-input/multiple-output (Massive-MIMO) applications.

Practicing engineers are expected to effectively work in teams and manage projects besides being capable of producing sound technical solutions. Project based learning allows students to improve their skills in issues such as team work and project management, and applying their knowledge in concrete situations. This paper describes an approach to Project Based Learning that has been recently introduced in a Master degree in Electronic and Telecommunications Engineering. In this course unit, students develop a project to solve a problem proposed by a company. A person from the company follows the project development, along with a faculty member. During the academic year 2018-19, students organized developed 14 projects, originating from 12 different companies. The outcome of this first edition is assessed using three data sources: academic data (assessment marks and approval rates); the University quality assurance enquiry; and a survey, developed specifically for “Industrial Project”. The results show that both students and supervisors agree that the course organization is adequate and capable of engaging students and participating companies.

This paper presents a complete design methodology, from behavioral modelling to lab prototyping and validation, of a Distributed Unit (DU) lower physical layer transmission chain, for Fifth Generation (5G) New Radio (NR) wireless communication technology. The case study presented follows a model-driven engineering and prototyping approach, starting with a high-level behavioral model, which is refined and validated in a iterative way, until an hardware implementation is obtained and validated. Fast prototyping is achieved through the adequate combination of languages (Matlab, Simulink and VHDL), simulation and FPGA-based synthesis and debug tools. Simulation-based validation is performed at different stages of the design flow, from behavioral descriptions using floating-point precision, to cycle-accurate models using fixed-point representations. The DU transmission chain supports currently the Frequency Range 1 (FR1) of 5G-NR with a configurable channel bandwidth up to 100 MHz. However, the implemented solution is flexible and modular supporting the configuration of different communication parameters and interfaces for next generation networks. This is achieved through the parametrization of the models and implementation into MPSoC devices to be connected to Software Defined Radio RF frontends, using an automated design flow. Since the complete design occupies less than 5% of the MPSoC resources, the integration of the uplink reception chain and the creation of multiple instances for communication diversity can be done.

According to the recent perspectives for the next generation of mobile networks (5G), future wireless communications will be able to support the operation of safety-critical systems, such as remote surgery or vehicle platooning. For that purpose, high reliability and availability values (> 99.999%), as well as low end-to-end delay (<; 1 ms), are included in the requirements specification. In order to achieve these goals, novel solutions will need to be introduced both at the communications devices and at the network protocols. Fault tolerance mechanisms are good candidates to attain such dependability attributes. In this paper, a medium guardian concept is proposed to guarantee fail-silent behavior, both in time and value domains, for the nodes of a wireless network. After a generic description of the wireless medium guardian concept, its application to the case of ETSI ITS-G5-based vehicular communications is demonstrated. In this way, the design and practical implementation of a medium guardian for real-time vehicular communications is reported, together with the experimental evaluation of this first prototype. The obtained results demonstrate the low latency of the fault detection mechanism and the effectiveness of the guardian in preventing error propagation to other nodes of the network.

This PhD work presents a potential architecture and implementation for an FPGA-based all digital antenna array transmitter for wireless radio communications. By enabling the design of antenna arrays without external Digital-to-Analog Converters (DACs), external upconversion stages and without complex layouts, the analog front-end can be summed up to just amplification, filtering and radiation.

This paper presents a timing analysis of an active replication scheme previously developed for the road-side units (RSUs) of infrastructure-based vehicular networks. This replication strategy aims to increase fault-tolerance and reliability of RSUs, which are the master nodes of real-time vehicular communications protocols, e.g. V-FTT. Nevertheless, the proposed solution is protocol independent and can be applied to other wireless communications domains. The obtained results show that this replication scheme introduces low delay in the recovery procedure of failed RSU nodes and a small overhead in the protocol communications. However, under specific circumstances it can allow nodes non-compliant with the deterministic protocol to interfere with the scheduled packet transmission. In order to avoid this, some alternative solutions are briefly discussed at the end of the paper.

Since today's networks use traditional centralized management systems, the management became costly with the growth in the number of network equipments and available services. It became then clear that it was necessary to distribute the central management responsibilities throughout the network equipments.

In this paper an original agile and wideband all-digital Software Defined Radio (SDR) receiver is presented. The analog-to-digital conversion is based on Pulse Width Modulation (PWM) and it is performed directly at the Radio Frequency (RF) stage. The system is implemented using the high speed differential input buffers of a medium range Field Programmable Gate Array (FPGA) as comparators to quantize the analog signal and generate the PWM representation. Simulation and measured results will be presented and evaluated in terms of Signal-to-Noise Ratio (SNR), Error Vector Magnitude (EVM), bandwidth and power efficiency. Briefly, this architecture allows an input bandwidth of almost 3GHz maintaining an EVM below 2,5% for a 4MHz signal.

This paper presents a laboratorial platform for the development and trial of C-RAN compliant features. As part of future mobile networks standardization, C-RAN is considered as an evolution of the current RAN, which inherent challenges represent an interesting topic of research among academic institutions and industry. The proposed testbed is intended to provide a cost-effective emulation of the high price and vendor-specific closed radio base station equipment such as BBU and RRH modules. Based on open FPGA platforms, it leads to a high level of flexibility according to user-defined configurations as well as it provides a high set of real-world deployments features, such as the optical CPRI interface, multi-mode and multi-band capabilities. Furthermore, due to its modularity it is targeted for a wide range of C-RAN applications and optimization scenarios such as CoMP, cloud processing and baseband signal compression.

This paper presents a solution to improve clinical triage with a network of Wireless Sensor Tags based on pulse oximeters. The wireless sensor measures vital signs on a patient and outputs an automated clinical analysis. A central unit monitors these readings for a large number of sensors and helps to coordinate a first aid team, providing updated information on clinical status and patient location, if a critical condition is identified. As a proof of concept, a small network, composed by a few number of such Wireless Sensor Tags was developed, to validate the sensor, node, network protocol behavior, in obtaining realtime physiological data. With low power consumption constraints, the system is able to provide updated information from tens to hundreds of network nodes.

This paper presents the architecture and implementation of an FPGA-based all digital transmitter for wireless radio communications. These transmitters allow a greater degree of flexibility for the carrier frequency, signal bandwidth and the use of simultaneous multiple-standards. Latest advances in the state-of-the-art in this emerging area are presented as well as the remaining issues to be solved and the proposed architecture to address some them.

All-digital radios allow the full digitalization of the radio system which poses an important step towards the complete software description of RF signals proposed in SDR. Using digital signal processing techniques and the integration of the radio into a single digital chip, it is expected that high flexibility in these systems will be fundamental for the next generation of wireless networks. In addition, FPGA-based architectures take advantage of the high and heterogeneous processing power of modern FPGAs as well as their dynamic configurability capabilities needed for highly flexible radio transceivers.

In this Ph.D. work it is intended to explore innovative agile and wideband FPGA-based Software Defined Radio (SDR) receiver architectures for future 5G wireless communications. This short paper presents some preliminary work in this area, including interesting results of an innovative SDR receiver. This new architecture implements the analog-to-digital conversion directly at RF stage based on Pulse Width Modulation (PWM). The system is implemented using the high speed differential input buffers of a medium range FPGA as a comparator. Simulation and measured results will be presented and evaluated in terms of Signal-to-Noise Ratio (SNR) and Error Vector Magnitude (EVM). Briefly, this architecture allows an input bandwidth of almost 3GHz maintaining an EVM below 2% for a 2MHz wide signal.

The medium access is regarded as being one of the most challenging issues to solve in order to provide de- terministic wireless communications in vehicular networks. It has been demonstrated that standard protocols fail to properly address this issue. The implementation of deterministic Medium Access Control (MAC) protocols is hampered by the fact that commercial devices do not allow modifications to the standard MAC mechanism, and the development of a device from scratch to implement one MAC scheme is an extremely laborious endeavor. However, over the last few years, the IT2S platform for vehicular communications has been developed and is now in a stage that allows implementation and testing of new solutions for the vehicular communications environment. This paper presents an overview of MAC mechanisms capable of providing deterministic real-time access and assesses the features a communications device should include in order to allow the implementation of these mechanisms. It then proposes an implementation of such features taking advantage of the white box access to the IT2S platform, which is not usually available in COTS devices.

This paper presents HDy Copilot, an Android application for accident detection integrated with multimodal alert dissemination, both via eCall and IEEE 802.11p. The proposed accident detection algorithm receives inputs from the vehicle, via ODB-II, and from the smartphone sensors, namely the accelerometer, the magnetometer and the gyroscope. The Android smartphone is also used as human machine interface, so that the driver can configure the application, receive road hazard warnings issued by other vehicles in the vicinity and cancel countdown procedures upon false accident detection. A prototype implementation was validated via laboratory tests.

This paper presents the architecture and implementation of an FPGA-based all digital transmitter with a baseband sampling rate of 1 GHz. Hardware complexity and operation frequency analysis are performed to find the best hardware topology to improve the transmitter performance. The used polyphase decomposition techniques for delta sigma modulators considerably improve the bandwidth and SNR figures of merit of state-of-the-art FPGA integrated RF transmitters. The experimental results obtained show the feasibility of this approach and the improvement in the signal modulator oversampling ratio, enabling higher bandwidth in all-digital transmitters.

In this paper an FPGA-based System-on-Chip (SoC) implementation of a flexible digital radio is presented and evaluated. The implemented transmitter is able to perform a direct up-conversion of a baseband signal to RF operating in the gigahertz frequency range as well as it enables the simultaneous transmission of two different carriers, each one having a different modulation, bandwidth, etc. The developed architecture is fully integrated into a single FPGA device and allows software programmability by including an embedded microprocessor for control operations. The high flexibility of this architecture allows to easily change the frequency of the carriers as also the spectral masks, making it interesting in the scope of white spaces exploration and for software radio-based applications.

This paper describes the advanced real-time processor architecture (ARPA) system-on-chip. The goal of this work is to create a technology independent and synthetizable system-on-chip (SoC) model for real-time applications. The main component of the SoC is a MIPS32-based RISC processor. It is implemented using a pipelined simultaneous multithreading structure that supports the execution of more than one thread or task at a time. The synergy between pipelining and simultaneous multithreading allows combining the exploration of Instruction level parallelism and task level parallelism, hide the context switching time and reduce the need of employing complex speculative execution techniques to improve the performance of the pipelined processor. A fundamental component of the ARPA SoC is the operating system coprocessor, which implements in hardware some of the operating systems functions, such as task scheduling, switching, communication and timing. The proposed architecture allows building flexible, high performance, time predictable and power efficient processors optimized for embedded real-time systems.

This paper suggests a novel architecture for a reconfigurable accelerator for computations over discrete vectors. The number of executed operations is limited but they can arbitrarily be chosen from a practically unlimited set of feasible operations. The software model and hardware implementations of the accelerator are discussed in detail.

The paper discusses some new hardware and software tools that can be used for the design of virtual circuits based on dynamically reconfigurable FPGAs. With the aid of these tools we can implement a system that requires some, hardware resources R/sub c/, on available hardware that has resources R/sub h/, where R/sub c/>R/sub h/. The main idea of the approach supported by these tools is the rational combination of FPGA capabilities with some proposed methods for producing a modifiable specification, together with a novel technique for architectural and logic synthesis, which has been incorporated into the new design environment.

No abstract available.