This paper presents the hardware implementation of a stereo vision core algorithm, that runs in real-time and is targeted at automotive applications. The algorithm is based on the sum of absolute differences (SAD) and computes the disparity map using 320 times 240 input images with a maximum disparity of 100 pixels. The hardware operates at a frequency of 65 MHz and achieves a frame rate of 425 fps by calculating the data highly parallel and pipelined. Thus an implemented and basically optimized software solution, running on an Intel Pentium 4 with 3 GHz clock frequency is 166 times outperformed.

Selecting an embedded hardware platform for image processing has a big influence on the achievable performance. This paper reports our work on a performance benchmark of different implementations of some low-level vision algorithms. The algorithms are implemented on both Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) high-speed embedded platforms. The target platforms are a TITMS320C6414 DSP and an Altera Stratix FPGA. The implementations are evaluated, compared and discussed. The DSP implementations outperform the FPGA implementations, but at the cost of spending all its resources to these tasks. FPGAs, however, are well suited to algorithms, which benefit from parallel execution.

Extending the dynamic range of digital imagers is a rather recent applied science, where some research has already been done since Europe launched the joint research program EUREKA in 1986. However, the limitations of the image sensors and the processing power of the embedded processing systems used (e.g. in digital cameras), in addition to higher cost factors, prevented these systems being fast and therefore applicable. Since there is a growing demand for driving assistance systems and observation systems, special care and research is required to immunize vision systems against changing physical daylight conditions. This paper discusses a grayscale image sensor hardware framework and a recently developed implementation for the proposed solution to extend the dynamic range of a linear complementary metal-oxide-semiconductor (CMOS) sensor. A suggestion is made for a very large scale integration (VLSI) hardware system, which is firstly simulated in ModelSIM. In respect of generic attributes, the interfaces to image sensors and storage locations are highly adaptable in this approach.

Sensor systems for robotics and autonomous systems usually require small-sized and power-aware dedicated solutions for their realization. Therefore, an embedded system is the first choice - but the drawback is weaker computing power compared to state-of-the-art PC-based systems. This paper describes our approach on "boosting" the computing power of embedded vision systems. Our system consists of a platform based on a digital signal processor (DSP) enhanced by an additional field programmable gate array (FPGA) used as a co-processor. In our novel approach called resource optimized co-processing, both the DSP and the FPGA are driven in parallel for the execution of crucial parts of the vision algorithms. Thereby, through efficient usage of system resources a significant increase of the system performance is possible. The approach and the achievable profit in computing power is outlined in the paper. Based on an example case - the realization of a robot soccer embedded vision sensor - the usefulness and the powerfulness of our approach is demonstrated. In this demo case, by applying resource optimized co-processing, the most crucial and computing-intensive function was executed twice as fast as before. Thus, we were able to fulfill the stringent real-time requirements of the vision system.