Demo Data from VLDB 2026 / reviewers in the wild / expert
Donald J. Criscione
dblp:48/2162
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1981
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 77% Integrated circuit design · 23% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Processor architecture and microarchitecture › microprocessor design › processor core design
control unit design |
0.0 | 1 | 1981 | A Hard Progammable Control Unit Design Using VLSI Technology · IEEE Trans. Computers 1981 |
Integrated circuit design
VLSI design |
0.0 | 1 | 1981 | A Hard Progammable Control Unit Design Using VLSI Technology · IEEE Trans. Computers 1981 |
Methods — techniques the papers use, named apart from their topics
microprogramming · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1981 | A Hard Progammable Control Unit Design Using VLSI TechnologyabstractMicroprogramming has become a widely used technique which brings versatility to the control unit of a digital system. However, since all microcommands contained in a microinstruction are changed simultaneously, this form of control requires the coding of all possible combinations of parallel commands as separate microinstructions. This causes the resulting microprograms to become space- and timewise inefficient and makes it very difficult to control and/or synchronize independent processes. A new approach to modeling and implementing the flow of control in hardware systems is presented in this paper. Here a control flow is realized by a set of independent control operators that pass control to each other according to the precedence relationships defined by the control function which is implemented. The detailed architecture of a VLSI chip to implement a control unit as a hard- programmable control unit (HPCU) is also given. An HPCU contains many independent control operators and allows mask-programmable connections to be made among the operators to implement any given control function. Examples included in the paper demonstrate the effectiveness of an HPCU in implementing complex parallel control flows. Bulent I. Dervisoglu, Donald J. Criscione |
IEEE Trans. Computers | 2 |