Demo Data from VLDB 2026 / reviewers in the wild / expert
Paolo Sipala
dblp:48/2263
· DBLP profile ↗
9ranked-venue papers
5as first author
0since 2021 · last 1990
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Theory of computation · 3 · 1 first-authorSystems, architecture and hardware · 2Software engineering, systems software and programming languages · 2 · 2 first-authorApplied, interdisciplinary, general and emerging computing · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Electronic design automation · 86% Storage systems · 8% Memory systems · 6% | |
| Theoretical computer science
1 paper |
Algorithms and data structures · 100% |
Topics — the 10 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 2 | 1987 | A Hierarchical Global Wiring Algorithm for Custom Chip Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 Minimum-Area Wiring for Slicing Structures · IEEE Trans. Computers 1987 |
Algorithms and data structures
analysis of algorithms |
0.0 | 1 | 1990 | Analytic Variations on the Common Subexpression Problem · ICALP 1990 |
Electronic design automation › physical design
floorplanning |
0.0 | 2 | 1987 | Minimum-Area Wiring for Slicing Structures · IEEE Trans. Computers 1987 A Hierarchical Global Wiring Algorithm for Custom Chip Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › physical design › routing
global routing |
0.0 | 1 | 1987 | A Hierarchical Global Wiring Algorithm for Custom Chip Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › physical design › routing › global routing
hierarchical global wiring |
0.0 | 1 | 1987 | A Hierarchical Global Wiring Algorithm for Custom Chip Design · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1987 |
Electronic design automation › physical design › floorplanning
slicing floorplan |
0.0 | 1 | 1987 | Minimum-Area Wiring for Slicing Structures · IEEE Trans. Computers 1987 |
Storage systems › data management
data structure storage |
0.0 | 1 | 1982 | Compact Storage of Binary Trees · ACM Trans. Program. Lang. Syst. 1982 |
Memory systems › memory management
memory allocation |
0.0 | 1 | 1981 | Optimum Cell Size for the Storage of Messages · IEEE Trans. Software Eng. 1981 |
Electronic design automation › design optimization
area optimization |
0.0 | 1 | 1987 | Minimum-Area Wiring for Slicing Structures · IEEE Trans. Computers 1987 |
Programming languages and type systems › functional programming
lisp |
0.0 | 1 | 1982 | Compact Storage of Binary Trees · ACM Trans. Program. Lang. Syst. 1982 |
Methods — techniques the papers use, named apart from their topics
analytic combinatorics · 0.0slicing tree · 0.0refinement · 0.0multiterminal net routing · 0.0hierarchical decomposition · 0.0mathematical optimization · 0.0closed-form derivation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1990 | Analytic Variations on the Common Subexpression Problem
Philippe Flajolet, Paolo Sipala, Jean-Marc Steyaert |
ICALP | 2 |
| 1988 | Efficient Implementation of Binary Trees in LISP SystemsabstractIn this paper, I consider how to implement the basic data structure of LISP programming, the binary tree. I show that, for the compact encoding of LISP trees, three-pointer cells are preferable to the conventional two-pointer ones. The result is one I reported previously, but here the analysis is done more elegantly, using the methods of probabilistic grammars. I also present a detailed implementation of LISP operators for the case in which multi-pointer cells are adopted. Paolo Sipala |
Comput. J. | 1 |
| 1987 | Minimum-Area Wiring for Slicing StructuresabstractIn this paper we consider the problem of optimal wiring of VLSI circuits. The topological placement of the circuit elements (macros) on the chip is assumed to have a special hierarchical structure, i.e., to be a slicing floorplan, represented by a binary (slicing) tree. Instead of the usual objective of minimum wire length, we consider the problem of minimizing the overall area of the wired floorplan. For the case of a single multiterminal net connecting n macros, we obtain a wiring algorithm of complexity O(nd), where d is the depth of the slicing tree. The case of several multiterminal nets is still under investigation. Wing K. Luk, Paolo Sipala, Chak-Kuen Wong |
IEEE Trans. Computers | 2 |
| 1987 | A Hierarchical Global Wiring Algorithm for Custom Chip DesignabstractWe present a global wiring algorithm used in a top-down physical design environment, i.e., macros are laid out after global wiring is done, and wires are allowed to pass through macros (the wiring-through model). The floorplan of the chip is in the form of a slicing structure. The algorithm is based on a hierarchical scheme. The final result is obtained through a series of refinement as the problem is recursively decomposed into a set of small-sized problems and then solved efficiently. The worst-case run-time for an arbitrary slicing tree (totally skewed) is O(M /sup 2/ N). When the floorplan is represented by a balanced slicing tree, the run-time of the overall algorithm is O(MN), where M is the number of macros and N the number of nets. The algorithm has been implemented in the C language and is used for chip designs. Experiments on both real and randomly generated designs show that the hierarchical router performs equally well as a flat global router in terms of wire length and wireability handling, but much faster in run-time (at least 10 times for an example with 100 macros and 1000 nets, and the gap being even larger for bigger-size problems). Wing K. Luk, Paolo Sipala, Markku Tamminen, Donald T. Tang, Lin S. Woo, Chak-Kuen Wong |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 1986 | Constructing Maximal Slicings from Geometry
Markku Tamminen, Wing K. Luk, Paolo Sipala, Lin S. Woo, Chak-Kuen Wong |
Acta Informatica | 3 |
| 1982 | Compact Storage of Binary TreesabstractStatistical measurements of the behavior of LISP programs have shown a marked asymmetry in the distribution of their data structures (binary trees).On the basis of a statistical model for such a distribution, we evaluate the expected storage cost of a representation of binary trees based on the use of k-pointer cells instead of conventional two-pointer ones.We conclude that LISP trees would be more efficiently encoded using three-pointer nodes. Paolo Sipala |
ACM Trans. Program. Lang. Syst. | 1 |
| 1981 | Optimum Cell Size for the Storage of MessagesabstractIn this paper we discuss a memory allocation problem first introduced by Wolman in [1] (see also [2]). A general solution formula is presented, from which closed form expressions for a few special cases may be easily derived. Paolo Sipala |
IEEE Trans. Software Eng. | 1 |
| 1977 | Remark on "Algorithm 408: A Sparse Matrix Package (Part I) [F4]"abstractNo abstract available. Paolo Sipala |
ACM Trans. Math. Softw. | 1 |
| 1969 | Formatting and display of ALGOL expressionsabstractA computer program is described which displays ALGOL arithmetic expressions in two-dimensional form on a line printer or a typesetter. Paolo Sipala |
Comput. J. | 1 |