This paper presents a new DC-coupled differential driver for 3D photonic electronic wafer-scale packaging. The DC-coupling between the driver's output and a Mach-Zehnder modulator (MZM), overcomes the limitations of on-chip bias-Ts and achieves wideband RF performance. For the biasing and impedance matching it uses off-chip inductors as RF chokes and two on-chip 50 Ω resistors in series with a capacitor as the driver's differential termination. The proposed driver has independent voltage supplies for the differential branches, and each branch can be tuned between 4 V and 6 V separately to account for different modulations format and fabrication tolerance of MZMs. The designed distributed driver is realized in a 0.25 μm SiGe:C BiCMOS technology, and shows a 3-dB bandwidth of 50 GHz, 100 Gb/s PAM4 eye diagram and state-of-the-art 6.3 pJ/bit power efficiency in post-layout simulation.

This work describes a method of implementing a fully-integrated ultra-low power (ULP) radio for wireless sensor networks (WSN). This is achieved using a specific medium access control (MAC) protocol, employing a duty- cycled wake-up radio and a crystal-less clock generator, and an ad-hoc modulation scheme (Impulse Radio) with a bandwidth of 17.7 MHz in the 2.4 GHz - ISM band. The total average power consumption is expected to be less than 100 muW.

In this paper, the many issues around the system and circuit design of advanced RF front ends for wireless RF applications will be discussed. After a short discussion on technology related issues, design choices linked to the different circuit/system solutions will be discussed.

Addresses the problems and solutions that are posed by the design of mixed-signal integrated systems on chip (SoC). These include problems in mixed-signal design methodologies and flows, problems in analog design productivity, as well as open problems in analog, mixed-signal and RF design, modeling and verification tools. The tutorial explains the problems that are posed by these mixed-signal/RF SoC designs, describes the solutions and their underlying methods that exist today and outlines the challenges that still remain to be solved at present. In the first part the design of analog and mixed-signal circuits is addressed, while the second part focuses on the specific problems raised by RF wireless circuits.

Article Share on High density capacitance structures in submicron CMOS for low power RF application Authors: Tirdad Sowlati Philips Research, 345 Scarborough Road, Briarcliff Manor, NY Philips Research, 345 Scarborough Road, Briarcliff Manor, NYView Profile , Vickram Vathulya Philips Research, 345 Scarborough Road, Briarcliff Manor, NY Philips Research, 345 Scarborough Road, Briarcliff Manor, NYView Profile , Domine Leenaerts Philips Research, Prof. Hostlaan4, 5656AA, Eindhoven, Netherlands Philips Research, Prof. Hostlaan4, 5656AA, Eindhoven, NetherlandsView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 243–246https://doi.org/10.1145/383082.383147Online:06 August 2001Publication History 2citation336DownloadsMetricsTotal Citations2Total Downloads336Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the system's database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

Article Free Access Share on A new efficient method for substrate-aware device-level placement (short paper) Authors: C. Lin Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, 5600 MB Department of Electrical Engineering, Eindhoven University of Technology, Eindhoven, 5600 MBView Profile , D. M. W. Leenaerts Philips Research Labs, Prof. Holstlaan 4, Eindhoven, 5656 AA Philips Research Labs, Prof. Holstlaan 4, Eindhoven, 5656 AAView Profile Authors Info & Claims ASP-DAC '00: Proceedings of the 2000 Asia and South Pacific Design Automation ConferenceJanuary 2000 Pages 533–536https://doi.org/10.1145/368434.368781Online:28 January 2000Publication History 6citation88DownloadsMetricsTotal Citations6Total Downloads88Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A method is proposed to obtain explicit expressions for the large signal behavior in nonlinear dynamic circuits. The method is also an extension to the solution method for linear dynamic complementary problems.

This paper introduces a new sequence pair algorithm which has a complexity lower than O(M/sup 1.25/), which is a significant improvement compared to the original O(M/sup 2/) algorithm. Furthermore, the new algorithm has complexity close to the theoretical lower bound. Experimental results, obtained with a straightforward implementation, confirm this improvement in complexity.

This paper presents an accurate switched-current multiplier, designed for 3.3 V supply voltage, performing 0.625 M multiplications per second with a maximum nonlinearity of 0.94%. The used technology is 2.4 /spl mu/m n-well CMOS. The power dissipation is lower than 0.3 mWatts.

DARWIN is a tool that is able to synthesize CMOS opamps, on the basis of a genetic algorithm.A randomly generated initial set of opamps evolves to a set in which the topologies as well as the transistor sizes of the opamps are adapted to the required performance specifications.Several design examples illustrate the behavior of DARWIN.

In this paper, a new architecture for cyclic algorithmic DA converters will be proposed. The upper bound for the maximum number of converted bits will be expressed in the mismatch error of the factor 1/2. It turns out that the number of relevant bits is twice the number achieved in the conventional technique under the same assumed mismatch error, without raising the conversion time above n-times a single bit conversion. An implementation in switched-current technique is treated.