We present an approach which addresses a fundamental scaling limitation for conventional switches. Instead of processing the data packets one by one, train queue processing groups multiple data packets together and processes them as one unit. There are two basic train queuing techniques, sequential train queuing and sequential-to-parallel train queuing. The sequential train queue processing can reduce the global switch processing frequency for the switch. The sequential-to-parallel train queue processing can reduce both the global switch processing frequency and data rate by using packet grouping and slicing mechanism. By employing train queuing techniques, a high bandwidth switch can be built and feasibly implemented.

We propose the multi-channel deflection crossbar (MCDC) as a promising architecture for broadband ATM switching under the realistic constraints imposed by VLSI technology. MCDC is an internally nonblocking, buffer efficient, crossbar based architecture. MCDC is also capable of multi-channel switching with cell sequence integrity preserved. Through a comparative study against a well-known ATM switch architecture, we show that the proposed MCDC architecture is able to incorporate a greater number of input channels and buffers for a given IC die size and requires a lower clocking rate.