As the semiconductor process technology advances into sub-10-nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for design rule violations (DRVs). Therefore, a machine-learning model for DRV prediction needs to consider both very high-resolution pin shape patterns and low-resolution layout information as input features. A new convolutional neural network technique, J-Net, is introduced for the prediction with mixed resolution features. This is a customized architecture that is flexible for handling various input and output resolution requirements. It can be applied at placement stage without using global routing information. This technique is evaluated on 12 industrial designs at a 7-nm technology node. The results show that the J-Net-based binary classifier can improve the true positive rate by 37%, 40%, and 7%, respectively, compared to extensions of three recent works, with similar false positive rates.

Double patterning is a widely used technique for sub-22nm. Among various double patterning techniques, Self-Aligned Double Patterning (SADP) is a promising technique for good mask overlay control. Based on SADP, a new set of standard cells (T-cells) are developed using thicker metal wires for stronger drive strength. By applying this kind of gates on critical paths, it helps to improve the design performance. However, a mixed design with T-cells and normal cells (N-cells) requires that T-cells are placed on circuit rows with thicker metal, and the normal cells are on the normal circuit rows. Therefore, a placer is needed to adjust the cells to the matched circuit rows. In this paper, a two-stage min-cost max-flow based legalization flow is presented to adjust N/T gate locations for a legal placement. The experimental results demonstrate the effectiveness and efficiency of our approach.

As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for DRC violations. Therefore, a machine learning model for DRC hotspot prediction needs to consider both very high-resolution pin shape patterns and low-resolution layout information as input features. A new convolutional neural network technique, J-Net, is introduced for the prediction with mixed resolution features. This is a customized architecture that is flexible for handling various input and output resolution requirements. It can be applied at placement stage without using global routing information. This technique is evaluated on 12 industrial designs at 7nm technology node. The results show that it can improve true positive rate by 37%, 40% and 14% respectively, compared to three recent works, with similar false positive rates.

The growing complexity and size of designs have driven chip implementation teams to adopt hierarchical design methodologies that divide-and-conquer the design closure task. Wherein, the large chip is partitioned into physical blocks with boundary constraints for physical synthesis which are then integrated at the top-level to achieve overall design closure. Each block could be further partitioned until the block sizes are manageable from a tool turnaround time perspective. A key aspect to efficient hierarchical design involves generation of realistic block-level timing budgets and physical constraints (contracts) to enable parallel implementation of each block. In a typical hierarchical design flow, these block-level contracts are created based on early estimations of timing and wiring from the floorplanning phase but evolve as the design progresses, often requiring several iterations of design integration to converge. High-performance designs require efficient contract management while allowing seamless design closure optimizations across levels of hierarchy. This talk will focus on some of the challenges in managing contracts with emphasis on the implications for physical synthesis tools used in hierarchical design closure.

In this paper we present a method for parameterized free space redistribution of a fragmented placement. The fragmentation problem arises in different contexts within the physical design automation, including post physical synthesis for filler cell insertion, incremental placement, timing optimization, and late mode ECO fix-ups. To address this problem, we apply a post-placement parameterized method of defragmentation. This method involves capturing a view of a given placement and modeling a dynamic programming problem to optimally maximize the amount of so-called useful free space as defined by a given set of parameters. The parameters act as constraints to preserve the row placement and order of the cells while minimizing the perturbation of the whole design for a successful timing and design closure. Experimental results demonstrate that by applying the proposed technique, on average, 9.7% increase in the number of inserted filler cells and 5.7% improvement in the success rate of incremental placement requests can be achieved with minimal or no impact on timing and wirelength. Moreover, when deployed in early mode buffering for timing optimization, this technique can result in 3% reduction in the number of paths with negative slacks.

We propose a new multilevel framework for large-scale placement called MAPLE that respects utilization constraints, handles movable macros and guides the transition between global and detailed placement. In this framework, optimization is adaptive to current placement conditions through a new density metric. As a baseline, we leverage a recently developed at quadratic optimization that is comparable to prior multilevel frameworks in quality and runtime. A novel component called Progressive Local Refinement (ProLR) helps mitigate disruptions in wirelength that we observed in leading placers. Our placer MAPLE outperforms published empirical results --- RQL, SimPL, mPL6, NTUPlace3, FastPlace3, Kraftwerk and APlace3 -- across the ISPD 2005 and ISPD 2006 benchmarks, in terms of official metrics of the respective contests.

Local routing congestion is becoming increasingly important as complex design rules make local pin access the bottleneck for modern designs and routers. Since congestion analysis based on global routing does not model these effects, routability-driven placement and physical synthesis fail to alleviate local congestion. This work models routing congestion at the placement level in order to apply local congestion mitigation. We propose a local congestion metric that computes a “routing-difficulty” score for every cell in the design library. To disperse local congestion, we apply a suite of detailed placement techniques called MILOR (Movement, cell Inflation and Legalization, and Optimization within a Row). Experimental results show that our techniques can significantly improve routing quality on real industry designs from 65, 45, and 32 nanometer technologies.

Timing-driven placement is a critical step in nanometer-scale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a commonly used technique. This paper shows that such an approach can improve timing, but often degrades wire length and routability. Another problem with existing timing-driven placers is inconsistencies in the definition of timing closure. Approaches using linear programming are forced to make assumptions about the timing models that simplify the problem. To truly do timing-driven placement, the placer must be able to make queries to a real timing analyzer with incremental capabilities. This paper describes an incremental timing-driven placer called ITOP. Using accurate timing from an industrial static timer, ITOP integrates incremental timing closure optimizations like buffering and repowering within placement to improve design timing without degrading wire length and routability.

Traditionally placement evaluation metrics have been based on wirelength and congestion measures and are independent of the logic network topology. However, the actual timing measure, which is used in a design closure loop, is path-based and dependent on the network topology. In this paper, we propose a design-topology aware metric that encapsulates the structural property of the circuit and physical goodness of the given placement. We present such a metric which is based on path monotonicity and an efficient method to compute this measure for a given placement. This method involves abstract path generation, clustering based region refinement and physical monotonicity analysis. Experimental results on real industry designs, using a commercial strength design closure flow, establish the usefulness of this metric in predicting the quality of a given placement with respect to design timing closure.