As we turn the corner into the new century, design is increasingly focused on single integrated circuit implementations of complete systems. Similar to alchemy in the middle ages, the design of a complex system onto an IC is an art and possibly an illusion understood by a very few. It is a complex search for an optimal answer which requires understanding the application, the system domain, digital function and control, and the fundamentals of circuits and IC fabrication technology. Due to the complexity of standards and processing, no one company understands or owns all of the needed technologies.

This paper reports on the development of a flexible 5-MBd equalized M-QAM testbed for high-speed wireless data communications. The unit operates in real time and was field tested in typical indoor environments. A total of 3600 independent experiments were conducted using the testbed where one of 4-, 16-, 64-QAM constellations were transmitted, and the performance as a function of adaptive equalization and antenna selection diversity was studied. The experimental results presented here help put previous simulation and analytical results into perspective and demonstrate some of the performance bounds associated with a practical implementation. The field trial results show that with only 10-mW of transmit power, reliable 10-Mbit/s data communication can take place in between rooms with a coverage radius of 17 m, and better than 15% outage at an uncoded bit error rate (BER) of 10/sup -3/. The addition of two-branch antenna selection diversity to the system would allow 10-Mbit/s transmission at better than 3% outage and 20-Mbit/s transmission at 10% outage in the same environment. Moreover, 30-Mbit/s data transmission is feasible when both the transmitter and receiver are located within the same room, albeit at higher outage levels. In general, the results demonstrate the tremendous impact that adaptive equalization can have on the achievable performance of indoor links. Average SNR was improved anywhere from 8 dB to 12 dB depending on the particular environment and data rate. The impact on the outage performance, however, was much more dramatic.

Adaptive antenna arrays provide wireless communication systems with larger service capacity and higher link quality through frequency reuse and cochannel-interference rejection. In practice, the propagation environment is nonideal with shadowing, severe stationary, and fast multipath fading. In this paper, the combination of adaptive antenna arrays and equalization techniques is employed to achieve reliable high-bit-rate wireless communications in a multipath, multiinterferer environment. A low-complexity receiver structure is investigated for the feasibility of portable wireless communications applications. The performance of the proposed receiver is analyzed in both outdoor and indoor multipath conditions. The simulations show that, although the adaptive beamformer is capable of cancelling long-delayed multipath reflections in the outdoor environment within its degrees of freedom, the adaptive equalizer is mandatory to compensate for the residual of the outdoor environment or the short-delayed multipath reflections of the indoor environment to achieve a high-quality link and high data rate. The digital circuits of the proposed receiver are estimated to perform 50 billion operations per second (GOPS) of digital signal processing functions, and the gate count is estimated to be 100 000 for a custom integrated circuit implementation.

An all digital-QAM system is studied here for high-speed data transmission on digital subscriber loops. All elements of the system have been fully investigated and their effects on overall system performance documented. In particular, the following issues have been explicitly addressed: utility of an adaptive error-prediction (noise-prediction) filter; equalizer size and convergence; blind equalization; choice of constellation size and center frequency; combined timing/carrier recovery; and the oversampling requirements of a numerically-controlled-oscillator (NCO) for potential use in the timing and carrier recovery loop. The paper relies on simulation results to investigate and quantify the overall interactions of the various blocks. Throughout the paper emphasis has been placed on reducing the complexity of the system for implementation on an integrated circuit (IC). It is expected that the information provided here will serve as a good starting point for an IC designer to start the implementation of a transceiver ASIC

A VLSI architecture for an all-digital binary phase shift keying (BPSK) direct-sequence (DS) spread spectrum (SS) intermediate frequency (IF) receiver is presented, and an in-depth performance analysis is given. The all-digital architecture incorporates a Costas loop for carrier recovery and a delay-locked loop for clock recovery. For the pseudorandom noise (PN) acquisition block, a robust energy detection scheme is proposed to reduce false PN locks over a broad range of signal-to-noise ratios. The proposed architecture is intended for use in the 902-928 MHz unlicensed spread spectrum radio band. A 100 kbs information rate and a 12.7 Mchips/second PN code rate are assumed. The IF center frequency is 12.7 MHz and the IF sampling rate is 50.8 Msamples/second, which is the Nyquist rate for the 25.4 MHz bandwidth signal. Finite wordlength effects have been simulated to optimize the architecture, thereby minimizing the chip area, and results of the finite wordlength simulations demonstrate that the chip architecture achieves a bit error rate performance within 1 dB of theory in an additive white Gaussian noise channel.>

A 70-MHz decision-feedback equalizer chip set using novel architecture and circuit design techniques that can accommodate a wide variety of modulation formats (QPSK, 16-, 64-, 256-QAM) is proposed. The equalizer is configurable into either a symbol-spaced or fractionally spaced structure. The CMOS chips are full cascadable to implement longer filter lengths without any speed degradation, and the coefficient updating circuitry for implementing the LMS algorithm is included on-chip.>

A universal architecture for decimation/interpolation digital filtering applications is proposed for custom VLSI implementation to accommodate real-time signal processing at throughput rates in excess of 100 MHz. The main innovation of this architecture is that it allows a single chip to selectively perform decimation or interpolation filtering with selectable conversion ratios of 2/sup 1/,2/sup 2/,. . .2/sup N/. The key feature of the proposed architecture is that a single decimate/interpolate-by-two half-band digital filter is used as the computational engine, and the output samples are simply recycled through the same filter after each decimation/interpolation stage for further filtering. A delicate timing allocation scheme for this half-band filter to be shared among each decimation/interpolation stage plays a critical role in allowing the filter to have selectable conversion ratios and still accommodate throughput rates in excess of 100 MHz.>

A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2- mu m CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3*4.3 mm/sup 2/, 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud.>

An optimization technique is presented for the design of multiplierless two-channel linear-phase finite-duration impulse-response (FIR) filter banks. It is shown to yield filter banks with good filtering performance and nearly perfect signal reconstruction. The design employs filters whose coefficients are represented by a canonic signed-digit (CSD) code. When applied to subband image coding this technique provides an easy way to design low-complexity analysis/synthesis filter banks for high-performance codecs. Examples concerning filter design and the application of such filters to subband image coding are given.>

An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25- mu m process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256*256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M-ary PSK and QAM.>