A linear arrangement problem, called the minmax mincut problem, emerging from circuit design is investigated. Its input is a series-parallel directed hypergraph (SPDH), and the output is a linear arrangement (and a layout). The primary objective is to minimize the longest path, and the secondary objective is to minimize the cutwidth. It is shown that cutwidth D, subject to longest path minimization, is affected by two terms: pattern number k and balancing number m. Also, k and m are both lower bounds on the cutwidth. An algorithm, running in linear time, produces layouts with cutwidths $D \leq 2(k+m)$. There exist examples with $k=\Omega (N)$, where N is the number of vertices; however, m is always O(log N). We show that every SPDH, after $local\ logic\ resynthesis$ (specifically, after reordering the serial paths), can be linearly placed with cutwidth D=O(log N). Simultaneously, its dual SPDH can be linearly placed with the same vertex order and with cutwidth D=O(log N). Therefore, after local resynthesis the area can be reduced by a factor of N/log N. Application to gate-matrix layout style is demonstrated.

We study the reproducing placement problem, which finds application in layout-driven logic synthesis. In each phase, a module (or gate) is decomposed into two (or more) simpler modules. The goal is to find a "good" placement in each phase. The problem, being iterative in nature, requires an iterative algorithm. In solving the RPP, we introduce the notion of minimum floating Steiner trees (MFST). We employ an MFST algorithm as a central step in solving the RPP. A Hanan-like theorem is established for the MFST problem, and two approximation algorithms are proposed. Experiments on commonly employed benchmarks verify the effectiveness of the proposed technique.

A linear arrangement problem, called the minmax mincut problem, emerging from circuit design is investigated. Its input is a series-parallel directed hypergraph, and the output is a linear arrangement (and a layout). The primary objective is to minimize the longest path, and the secondary objective is to minimize the cutwidth. It is shown that cutwidth D, subject to longest path minimization, is affected by pattern number k, which is also a lower bound on the cutwidth but not a tight one. There exist examples with k=/spl Omega/(N), where N is the number of vertices. We propose an algorithm producing cutwidths D=O(k+log N). We also show that every series-parallel directed hypergraph, after reordering the serial paths, can be linearly placed with cutwidth D=O(log N). Simultaneously, its dual series-parallel directed hypergraph can be linearly placed with the same vertex order and with cutwidth D=O(log N). Applications on gate-matrix layout style in very large-scale-integrated (VLSI) CMOS circuit design are demonstrated.