Wilm E. Donath

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dblp:48/5892 · also William E. Donath · DBLP profile ↗

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10ranked-venue papers

4as first author

0since 2021 · last 2002

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 10 · 4 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

5 papers

High-performance computing · 55% Integrated circuit design · 28% Electronic design automation · 17%

Topics — the 11 heaviest of 11, each with the papers that count most for it

Topic	Papers	Last	Evidence papers
High-performance computing › supercomputing bluegene/l	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
High-performance computing supercomputing	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Integrated circuit design system-on-chip	1	2002	An overview of the BlueGene/L Supercomputer · SC 2002
Electronic design automation physical design	3	1990	Timing Driven Placement Using Complete Path Delays · DAC 1990 Complexity theory and design automation · DAC 1980 Prediction of wiring space requirements for LSI · DAC 1977
Electronic design automation › physical design › placement timing-driven placement	1	1990	Timing Driven Placement Using Complete Path Delays · DAC 1990
Electronic design automation hardware verification and test	2	1980	9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits · IEEE Trans. Computers 1978 Complexity theory and design automation · DAC 1980
Electronic design automation › hardware verification and test test generation	2	1980	9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits · IEEE Trans. Computers 1978 Complexity theory and design automation · DAC 1980
Electronic design automation › hardware verification and test › test generation path sensitization	1	1978	9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits · IEEE Trans. Computers 1978
Electronic design automation › physical design wire space estimation	1	1977	Prediction of wiring space requirements for LSI · DAC 1977
Integrated circuit design digital circuit design	1	1977	Prediction of wiring space requirements for LSI · DAC 1977
Integrated circuit design VLSI design	1	1977	Prediction of wiring space requirements for LSI · DAC 1977

Methods — techniques the papers use, named apart from their topics

system architecture design · 0.0performance scaling studies · 0.0critical path timing evaluation · 0.0complexity theory · 0.0nine-valued logic calculus · 0.0

Year	Publication	Venue	Position
2002	Blue Gene/L, a System-On-A-Chip abstract Summary form only given. Large powerful networks coupled to state-of-the-art processors have traditionally dominated supercomputing. As technology advances, this approach is likely to be challenged by a more cost-effective System-On-A-Chip approach, with higher levels of system integration. The scalability of applications to architectures with tens to hundreds of thousands of processors is critical to the success of this approach. Significant progress has been made in mapping numerous compute-intensive applications, many of them grand challenges, to parallel architectures. Applications hoping to efficiently execute on future supercomputers of any architecture must be coded in a manner consistent with an enormous degree of parallelism. The BG/L program is developing a peak nominal 180 TFLOPS (360 TFLOPS for some applications) supercomputer to serve a broad range of science applications. BG/L generalizes QCDOC, the first System-On-A-Chip supercomputer that is expected in 2003. BG/L consists of 65,536 nodes, and contains five integrated networks: a 3D torus, a combining tree, a Gb Ethernet network, barrier/global interrupt network and JTAG. George S. Almási, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, Alina Deutsch, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Joseph Gagliano, Alan Gara, Robert S. Germain, Mark Giampapa, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, T. Jamal-Eddine, Gerard V. Kopcsay, Alphonso P. Lanzetta, Derek Lieber, M. Lu, Mark P. Mendell, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Rick A. Rand, Richard D. Regan, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, Sarabjeet Singh, Peilin Song, Burkhard D. Steinmacher-Burow, Karin Strauss, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, J. Brown, Thomas A. Liebsch, A. Schram, G. Ulsh	CLUSTER	20
2002	An overview of the BlueGene/L Supercomputer abstract This paper gives an overview of the BlueGene/L Supercomputer. This is a jointly funded research partnership between IBM and the Lawrence Livermore National Laboratory as part of the United States Department of Energy ASCI Advanced Architecture Research Program. Application performance and scaling studies have recently been initiated with partners at a number of academic and government institutions,including the San Diego Supercomputer Center and the California Institute of Technology. This massively parallel system of 65,536 nodes is based on a new architecture that exploits system-on-a-chip technology to deliver target peak processing power of 360 teraFLOPS (trillion floating-point operations per second). The machine is scheduled to be operational in the 2004-2005 time frame, at price/performance and power consumption/performance targets unobtainable with conventional architectures. Narasimha R. Adiga, Gheorghe Almási 0001, George S. Almási, Yariv Aridor, Rajkishore Barik, Daniel K. Beece, Ralph Bellofatto, Gyan Bhanot, Randy Bickford, Matthias A. Blumrich, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Waiman Chan, Luis Ceze, Paul Coteus, Siddhartha Chatterjee, Dong Chen 0005, George L.-T. Chiu, Thomas M. Cipolla, Paul Crumley, K. M. Desai, Alina Deutsch, Tamar Domany, Marc Boris Dombrowa, Wilm E. Donath, Maria Eleftheriou, C. Christopher Erway, J. Esch, Blake G. Fitch, Joseph Gagliano, Alan Gara, Rahul Garg 0001, Robert S. Germain, Mark Giampapa, Balaji Gopalsamy, John A. Gunnels, Manish Gupta 0002, Fred G. Gustavson, Shawn Hall, Ruud A. Haring, David F. Heidel, Philip Heidelberger, Lorraine M. Herger, Dirk Hoenicke, R. D. Jackson, T. Jamal-Eddine, Gerard V. Kopcsay, Elie Krevat, Manish P. Kurhekar, Alphonso P. Lanzetta, Derek Lieber, L. K. Liu, M. Lu, Mark P. Mendell, A. Misra, Yosef Moatti, Lawrence S. Mok, José E. Moreira, Ben J. Nathanson, Matthew Newton, Martin Ohmacht, Adam J. Oliner, Vinayaka Pandit, R. B. Pudota, Rick A. Rand, Richard D. Regan, Bradley Rubin, Albert E. Ruehli, Silvius Vasile Rus, Ramendra K. Sahoo, Alda Sanomiya, Eugen Schenfeld, M. Sharma, Edi Shmueli, Sarabjeet Singh, Peilin Song, Vijay Srinivasan, Burkhard D. Steinmacher-Burow, Karin Strauss, Christopher W. Surovic, Richard A. Swetz, Todd Takken, R. Brett Tremaine, Mickey Tsao, Arun R. Umamaheshwaran, P. Verma, Pavlos Vranas, T. J. Christopher Ward, Michael E. Wazlowski, W. Barrett, C. Engel, B. Drehmel, B. Hilgart, D. Hill, F. Kasemkhani, David J. Krolak, Chun-Tao Li 0001, Thomas A. Liebsch, James A. Marcella, A. Muff, A. Okomo, M. Rouse, A. Schram, M. Tubbs, G. Ulsh, Charles D. Wait, J. Wittrup, Myung Bae, Kenneth A. Dockser, Lynn Kissel, Mark K. Seager, Jeffrey S. Vetter, K. Yates	SC	27
2001	Demonstrating the scalability of a molecular dynamics application on a Petaflop computer abstract The IBM Blue Gene project has endeavored into the development of a cellular architecture computer with millions of concurrent threads of execution. One of the major challenges of this project is demonstrating that applications can successfully exploit this massive amount of parallelism. Starting from the sequential version of a well known molecular dynamics code, we developed a new application that exploits the multiple levels of parallelism in the Blue Gene cellular architecture. We perform both analytical and simulation studies of the behavior of this application when executed on a very large number of threads. As a result, we demonstrate that this class of applications can execute efficiently on a large cellular machine. George S. Almási, Calin Cascaval, José G. Castaños, Monty Denneau, Wilm E. Donath, Maria Eleftheriou, Mark Giampapa, C. T. Howard Ho, Derek Lieber, José E. Moreira, Dennis M. Newns, Marc Snir, Henry S. Warren Jr.	ICS	5
2000	Transformational Placement and Synthesis abstract Novel methodology and algorithms to seamlessly integrate logic synthesis and physical placement through a transformational approach are presented. Contrary to most placement algorithms that minimize a global cost function based on an abstract representation of the design, we decomposed the placement function into a set of transforms and coupled them directly with incremental timing, noise, and/or power analyzers. This coupling results in a direct and more accurate feedback on optimizations for placement actions. These placement transforms are then integrated with traditional logic synthesis transforms leading to a converging set of optimizations based on the concurrent manipulation of boolean, electrical, as well as physical data. Experimental results indicate that the proposed approach creates an efficient converging design flow that eliminates placement and synthesis iteration. It results in timing improvements, and maintains other global placement measures such as wire congestion and wire length. The flexibility of the transformational approach allows us to easily add, extend and support more sophisticated algorithms that involve critical as well as non-critical regions and target a variety of metrics including noise, yield and manufacturability:. Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul G. Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty	DATE	1
2000	The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only) abstract No abstract available. Patrick Groeneveld, Jacob Greidinger, J. George Janac, Wilm E. Donath	ISPD	4
1999	Performance Driven Optimization of Network Length in Physical Placement abstract A novel technique to significantly improve the performance of a design by the movement of sets of gates during or after timing driven placement is proposed. A method to identify optimal set of circuit (gate) movements to enhance timing is presented. Experimental results with a min-cut placement tool indicate that the proposed approach of direct manipulation of circuit locations, significantly improves the timing of large partitions of a chip. Wilm E. Donath, Prabhakar Kudva, Lakshmi N. Reddy	ICCD	1
1990	Timing Driven Placement Using Complete Path Delays abstract The Timing Drive Placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required. Wilm E. Donath, Reini J. Norman, Bhuwan K. Agrawal, Stephen E. Bello, Sang-Yong Han, Jerome M. Kurtzberg, Paul Lowy, Roger I. McMillan	DAC	1
1980	Complexity theory and design automation abstract Complexity Theory is discussed and its relationship to Physical Design (i.e. Placement/Wiring) and Test Pattern Generation is shown and developed. Wilm E. Donath	DAC	1
1978	9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits abstract An algorithm for generating test patterns for combinational circuits has been developed and programmed. The algorithm is definitive and finds a test for all faults including those that require multiple paths to be sensitized, by sensitizing a single path at a time and trying at most each single path. This is achieved by using a new calculus based on nine values (0,1,D,D̄,0/D,0/D̄, 1/D,1/D̄,U). One path is deliberately sensitized while the alternative paths are assigned values which permit the option of desensitizing or sensitizing them as the sensitized path is developed. Experimental results are presented for a variety of cases. Charles W. Cha, Wilm E. Donath, Füsun Özgüner	IEEE Trans. Computers	2
1977	Prediction of wiring space requirements for LSI William R. Heller, W. F. Michail, Wilm E. Donath	DAC	3