The development of modern heterogeneous systems requires early integration of the various domains to improve and verify the design. Heterogeneous virtual prototypes are a key enabler to reach this goal. In order to efficiently support the development, their high simulation speed is of utmost importance. This article introduces measures to speed-up SystemC analog/mixed-signal (AMS) simulations which are commonly used to simulate the AMS part jointly with the digital prototype in SystemC. Two approaches to integrate variable-step ordinary differential equation solvers into the simulation semantics of SystemC AMS are presented. Both of them avoid global backtracking. One is well suited for feedback loops and the other is favorable for systems dynamically reacting onto events. Moreover, a timestep quantization is developed that overcomes the recurrent matrix inversion bottleneck of variable-step implicit solvers. A similar method is then used to increase the simulation speed of electrical linear network models with high switching activity. Various experiments from the context of smart sensors are presented which prove the effectiveness for enhancing the simulation speed.

The analog/mixed signal extensions to SystemC effectively tackle the needs for heterogeneous system integration using virtual prototyping. However, they introduce the inherent trade-off between accuracy and performance due to the discrete timestep. Besides the discrete-time scheduler, analog solvers are used within SystemC-AMS to solve linear ordinary differential equations (ODEs). In this paper, we derive two methodologies to integrate adaptive ODE solvers into SystemC-AMS that estimate the optimal timestep based on error control. The main advantage of the approaches is the avoidance of time-consuming global backtracking. Instead, they fit well into the execution semantics and scheduling approach of SystemC-AMS. A detailed comparison of both integration schemes is given and they are evaluated using a MEMS accelerometer as classical example of a heterogeneous system.

We present a flow to reuse system-level analog/mixed-signal (AMS) models developed in MATLAB/Simulink for the extension of virtual prototypes in SystemC. To prevent time-consuming co-simulation, our flow translates the Simulink model into an equivalent SystemC-AMS model. Translation is supported either by wrapping code generated by MATLAB's Embedded Coder or by instantiating previously generated models. Thus, a one-to-one mapping of the model's hierarchy is possible which allows deep insights into the architecture and good traceability. The conducted case study on an accelerometer model shows the applicability of our approach. The generated hierarchical model is half as fast as a monolithic version but allows better observability and traceability of the system. It is tens of times faster than simulation in Simulink. The extended virtual prototype aims to support software engineers during development and validation of firmware in smart sensors.

The growing number of ultra-low power sensor applications drives the processing requirements "on-the-edge" and increases the demand for smart sensors, which implement signal processing and algorithmic features in firmware. Virtual prototyping in SystemC has become a major field of interest to validate the firmware and allow a seamless integration. However, the capability of SystemC is limited to discrete-time applications and cannot handle the full sensor system including its analog front end and mechanical part. Consequently, the firmware validation is often limited to oversimplified scenarios. In this paper, we present a virtual system prototype (VSP) using SystemC and its analog/mixed-signal (AMS) extensions which permits the validation of complex firmware features with tight interaction to the sensor element. The key benefit of this approach is an improved controllability and observability during the sensor firmware development even in early design phases. An industrial case study of a MEMS accelerometer and gyroscope is used throughout the paper to illustrate the proposed approach. A performance analysis proves the pracitcal relevance of our full-stack VSP as the simulation time is increased by a factor less than five compared to a pure SystemC approach without any functionality in the analog or physical domain.

In sensor-based activity recognition often huge amounts of data have to be acquired from multiple sensors, which need to be communicated for further processing. When using wireless sensor nodes, energy efficiency is of outstanding importance, since it directly influences the time until the battery needs to be recharged. However, communicating a huge amount of sensor data over wireless interfaces causes high energy consumption as well. Furthermore, the host controller receiving the sensor data is hindered of using its low power modes, as it needs to be woken up more frequently as well. In the paper at hand, we introduce our approach of reducing energy consumption of sensor nodes in online activity recognition scenarios by calculating the feature extraction on the sensor subsystem itself. By doing so, we can reduce the output rate of the sensor which enables the host controller to stay in its low power modes for longer periods. Additionally, this approach drastically reduces the amount of data to be transmitted over wireless interfaces, which further improves energy consumption. In our experiments, the proposed approach reduces the energy consumption of a sensor node by up to 33 %.

As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL-centric framework it follows the concept of non-intrusiveness. In this paper, we discuss in detail the concepts of design elaboration into the scalable design model and present an evaluation of the model for static analysis as one of the back-end applications. Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects.

Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainability improve productivity. However, writing good HLMs for complex systems is still a challenging task. In the context of network controller design, modeling complexity has two major sources: (1) the functionality to handle a single connection, and (2) the number of connections to be handled in parallel. In this paper, we will propose an efficient actor-oriented modeling approach for complex systems by (1) integrating hierarchical FSMs into dynamic dataflow models, and (2) providing new channel types to allow concurrent processing of multiple connections. We will show the applicability of our proposed modeling approach to real-world system designs by presenting results from modeling and simulating a network controller for the Parallel Sysplex architecture used in IBM System z mainframes.

We propose a framework, called virtual processing components (VPC) that permits the modeling and simulation of multiple processors running arbitrary scheduling strategies in SystemC. The granularity is given by task accuracy that guarantees a small simulation overhead

Concurrent test features are available in SoC testers to increase ATE throughput. To exploit these new features, design modifications are necessary. In a case study, these modifications were applied to the open source LEON SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several embedded cores. The concurrent test of LEON was performed on an SoC tester. The gain in test application time and area costs are quantified and obstacles in the design flow for concurrent test are discussed.

Testing logic cores of a system-on-a-chip causes a high test data volume which has to be stored on the external automatic test equipment (ATE), a high bandwidth requirement between ATE and the chip under test implying the need for high-speed ATE. This paper reduces these requirements by reusing embedded cores during test mode as embedded testers, Hard, firm, and soft cores may be reused, since only the functionality of the core in system mode is used.

An automatic test pattern generation (ATPG) method is presented for a scan-based test architecture which minimizes ATE storage requirements and reduces the bandwidth between the automatic test equipment (ATE) and the chip under test. To generate tailored deterministic test patterns, a standard ATPG tool performing dynamic compaction and allowing constraints on circuit inputs is used. The combination of an appropriate test architecture and the tailored test patterns reduces the test data volume up to two orders of magnitude compared with standard compacted test sets.

Most built-in self test (BIST) solutions require specialized test pattern generation hardware which may introduce significant area overhead and performance degradation. Recently, some authors proposed test pattern generation on chip by means of functional units also used in system mode like adders or multipliers. These schemes generate pseudo-random or pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under test contains random pattern resistant faults a deterministic test pattern generator is necessary to obtain complete fault coverage. In this paper it is shown that a deterministic test set can be encoded as initial values of an accumulator based structure, and all testable faults can be detected within a given test length by carefully selecting the seeds of the accumulator. A ROM is added for storing the seeds, and the control logic of the accumulator is modified. In most cases the size of the ROM is less than the size required by traditional LFSR-based reseeding approaches.