The most widely used positioning system today is the GPS (Global Positioning System), which has many commercial, civil and military applications, being present in most smartphones. However, this system does not perform well in indoor locations, which poses a constraint for the positioning task on environments like shopping malls, office buildings, and other public places. In this context, WLAN positioning systems based on fingerprinting have attracted a lot of attention as a promising approach for indoor localization while using the existing infrastructure. This paper contributes to this field by presenting a methodology for developing WLAN positioning systems using genetic algorithms and neural networks. The fitness function of the genetic algorithm is based on the generalization capabilities of the network for test points that are not included in the training set. By using this approach, we have achieved state-of-the-art results with few parameters, and our method has shown to be less prone to overfitting than other techniques in the literature, showing better generalization in points that are not recorded on the radio map.

In this paper, we present an ensemble strategy for haplotype inference problem. The proposed approach generates an ensemble solution from several haplotype matrices yielded by a non-deterministic algorithm. We performed extensive experiments and statistical performance evaluation. Besides the inference accuracy based on Switch Error, our analysis controls the execution time as well. The results show that the proposed method: (1) generates more accurate solutions compared to the existing strategies, (2) improves the precision of haplotyping techniques, such as fastPHASE, Beagle, and Mach, and (3) the Beagle based ensemble produced solutions with quality comparable to the more accurate but more computing intensive method: fastPHASE.

Scene text character recognition is a challenging task in Computer Vision since natural scene images usually have cluttered background and the character's size, font, orientation, texture, brightness, and alignment in the picture are variable and non-predictable. Furthermore, most systems including scene text character recognition are usually embedded in a system on a chip (SoC), which has critical requirements, such as low latency, low area, mobility, and flexibility, at the same time that they require high accuracy. In this context, in this work we propose a heterogeneous system for embedded applications with time, area and power constraints, that combines hardware and software to accelerate a technique for scene text character recognition, based on Histogram of Oriented Gradients (HOG) for feature extraction and a neural network Extreme Learning Machine (ELM) as a classifier. The system was prototyped and experimented in the Terasic embedded platform DE2i-150 and the results showed that the system has accuracy of 65.5% in the Chars74k-15 dataset and is able to process up to 11 frames per second, having a good trade-off between processing time and accuracy in embedded environments. Moreover, it occupies only 11% logic elements of the Altera Cyclone IV FPGA, enabling its use in embedded systems.

Prefetching technique is an effective approach to mitigate a well-known problem in multicore processors: the gap between computing and data access performance. Data prefetching goal is to anticipate data to CPU by retrieving data from memory and loading it into cache memory before the CPU request, reducing the miss rate and processor's penalty. In NoC-based multiprocessor systems, prefetching efficiency is even more critical to system performance, since memory access time depends on distance between the requesting processor and memory storing data, and also on the network traffic. This work proposes a temporized data prefetching mechanism that aims to minimize penalty in NoC-based multiprocessor. The proposed technique uses a proactive process initiated by the requesting processor to prefetch data from memory and load into local cache. The time to prefetch data is predicted based on cache miss history of each processor and NoC's traffic information. In experiments with 16 cores, the proposed algorithm successfully reduced the processors penalty in 6.25% on average and up to 29% when compared to an event-based technique.

The comparison of DNA sequences is a classic problem in molecular biology. Forensic applications uses this comparison for personal identication. For instance, in the USA, the CODIS system has today 14.9 million DNA proles stored on its database. To accelerate the recurrent task to query into similar databases, this work presents a hardware acderator for the parallel alignment of multiple DNA sequences, aiming for the maximum throughput Each of these alignments is done using the Needleman-Wunsch algorithm which represents an optimal global technique for measuring the similarity between DNA sequences. The proposed accelerator architecture optimizes the use of hardware resources, the data access strategy and, as a result, memory bandwidth. The experiments were conducted using a synthetic DNA database with 8 million individuals, in which, each of them is represented using a set of 15 sequences with a length of 240 nucleotides. In this case study, a prototype of the proposed hardware accelerator using a single Stratix IV FPGA is running at the frequency of 280MHz and outperforms by tens of times consolidated software applications like SWIPE and FASTA which are running in a high performance GPP platform, as well as optimized GPU implementation in OpenCL.

RISC-V is an open-source instruction set-architecture, designed to support customized extensions and architectures. This paper presents an instruction-set extension to the RISC-V ISA, idealized for software-defined radio applications. The custom instructions perform complex-number arithmetic, tailored for complex or quadrature modulation and baseband processing, and can perform one complex multiply-accumulate per cycle. The proposed system architecture includes the processor core, a WISHBONE bus interconnection, IO and peripherals, and was targeted to an Altera Cyclone III FPGA, achieving 0.9 DMIPS/MHz without the use of any compiler optimizations.

Due to the constant growth of the embedded systems complexity and the increasing number of mobile devices, there is a increasing demand for low power multiprocessor platforms. It is known that the cache memory contributes with a representative percentage of energy consumption of a MPSoC processor, so that it is very important to use an optimal cache configuration for an embedded application in order to obtain low power consumption satisfying performance constraints. We propose an approach for cache design space exploration for embedded applications on MPSoCs platforms based on the multi-objective Artificial Bee Colony (ABC) algorithm. The proposed approach, called AbcDE, uses DoE analysis to reduce the design space exploration for finding the cache configuration that improves performance and power consumption. The proposed cache design space exploration approach has been evaluated using applications of Splash2 (FFT, Radix and Matrix multiplication) and Mibench benchmarks (Dijkstra). As a result, a L1 cache configuration into a low-power Pareto front has been obtained with a reduction of 42.3% in the exploration time. The mean number of simulations is 40.4% lower when compared with the original multi-objective ABC algorithm. All results were obtained for a 4-core processor platform.

Extreme Value Theory (EVT) is a powerful statistical framework for estimating maximum values of random variables and has recently been applied for deriving probabilistic bounds on task execution times (pWCET). Task execution time data are collected from measurements and the maximum measured values are fit to an extreme value model. In this paper we provide a careful study on the applicability and effectiveness of EVT in this application field. The study is based on extensive experiments for which we have designed an embedded platform equipped with random cache of configurable sizes. Based on evidences of the experiments, we provide the following contributions: we give a new definition of pWCET that conforms with the fact that pWCET estimates depend on input data distribution used during analysis, we show that using the Generalized Extreme Value (GEV) distribution is necessary since the more restrictive modeling, based on the Gumbel distribution, may yield unsafe or over-estimated values of pWCET, we confirm that hardware randomization favors the applicability of EVT, although it does not ensure it since the distribution of maxima for execution time data are not guaranteed to be analyzable via EVT.

The quantity of computing application that interacts with users through gesture or body motion has been growing. Among these applications is the sign language recognizer used to help hearing impaired people. This work proposes an architecture able to recognize Brazilian sign language (LIBRAS) in an embedded platform. The system focuses on a simple feature from 'finger spelling expressions' represented by a series of hands gestural images, and uses the Extreme Learning Machine network to classify them. The proposed structure uses camera images only and does not need any gloves or sensors. The obtained results are 5 times faster and 16 times better than classical approaches.

Due to the large contribution of the memory subsystem to total system power, the memory subsystem is highly amenable to customization for reduced power/energy and/or improved performance. Cache parameters such as total size, line size, and associativity can be specialized to the needs of an application for system optimization. In order to determine the best values for cache parameters, most methodologies utilize repetitious application execution to individually analyze each configuration explored. In this paper we propose a simplified yet efficient technique to accurately estimate the miss rate of many different cache configurations in just one single-pass of execution. The approach utilizes simple data structures in the form of a multi-layered table and elementary bitwise operations to capture the locality characteristics of an application's addressing behavior. The proposed technique intends to ease miss rate estimation and reduce cache exploration time.

We introduce a new non-intrusive on-chip cache-tuning hardware module capable of accurately predicting the best configuration of a configurable cache for an executing application. Previous dynamic cache tuning approaches change the cache configuration several times as part of the tuning search process, executing the application using inferior configurations and temporarily causing energy and performance overhead. The introduced tuner uses a different approach, which non-intrusively collects data on addresses issued by the microprocessor, analyzes that data to predict the best cache configuration, and then updates the cache to the new best configuration in "one-shot", without ever having to examine inferior configurations. The result is less energy and less performance overhead, meaning that cache tuning can be applied more frequently. We show through experiments that the one-shot cache tuner can reduce memory-access related energy for instructions by 35% and comes within 4% of a previous intrusive approach, and results in 4.6 times less energy overhead and a 7.7 times speedup in tuning time compared to a previous intrusive approach, at the main expense of 12% larger size

Numerous variations of configurable caches, having variable parameters like total size, line size, and associativity, have been proposed in commercial microprocessors in recent years. Tuning a configurable cache to a target application has been shown to reduce memory-access power by over 50%. However, searching the configuration space for the best configuration can require much time or power, even when using recent cache tuning heuristics. We sought to determine, for a particular domain of applications, the smallest subset of cache configurations that would still enable effective tuning. For a suite of 34 benchmarks and a cache with 18 possible configurations, we determine through an exhaustive search of all possible subsets, that only 3 or 4 candidate configurations are necessary to support tuning. We introduce a new heuristic, adapted from an efficient and effective heuristic developed for data mining, to quickly determine the best configurations for any sized subset, with near optimal results. We then consider a configurable cache with 17,640 possible configurations and improve our heuristic to include a pre-pruning step, yielding near optimal tuning results. We conclude that only 3 or 4 possible cache configurations are needed to offer a near optimal configuration for every benchmark in our suite - resulting in a 91% reduction in design space exploration time over a state-of-the-art cache tuning heuristic.

Configurable cache tuning architectures for embedded systems applications can dramatically reduce energy consumption. Existing state-of-the-art heuristics to efficiently explore large configurable cache design space has aimed at finding the cache configuration that yields the minimal energy consumption. However, as energy-driven cache optimizations may reach great energy reduction, the overall system performance is often penalized by considering only a single-metric energy cost function. In this work, we propose an automated exploration mechanism for adjusting two-level cache hierarchies in order to reduce energy consumption for embedded applications, by keeping up the high performance computing. In our experiments, we applied our heuristic to 12 different benchmarks from the MiBench. The results show an average reduction of about 41% in the energy consumption for instruction caches when compared to existing heuristics and a reduction by about 25% the number of cycles needed to execute a given application.

It is a challenge to provide an efficient healthcare service for countries with continental dimensions. Mechanisms for a more efficient and better attendance of patients are necessary due to the increasing costs of health care systems. This work proposes the development of a system for monitoring vital signs (including ECG) through PDAs. Therefore, this has made possible the local attendance of patients by medical practitioners (here called health agents) with the support of specialist's physicians through a second opinion system. The proposed approach supports: recording and visualization of ECG waveforms. Moreover, patient's information can be transmitted to and from a remote health care server. In order to make easier the use by doctors and health agents, a user-friendly graphical interface has been developed. Methods for an efficient data access have been also developed to cope with storage constraints of PDAs.

This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to capture the processor description as well as the memory subsystem configuration, this environment offers support for system-level specification, intended for platform-based design. As a case study, it is presented the memory architecture exploration for a simple image processing application, yet a more robust environment evaluation is performed through the execution of some real-world benchmarks.

We present the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, programmable systems composed by processor and memories may be rapidly simulated making use of ArchC, an architecture description language (ADL) based on SystemC. Initially designed to model processor architectures, ArchC was extended to support a more detailed description of the memory subsystem, allowing the design space exploration of the whole programmable system. As an example, it is shown an image processing application, running on a SPARC-V8 processor-based architecture, which had its memory organization adjusted to minimize cache misses.

Due to design constraints, many digital systems are implemented as mixed hardware and software components. An informal choice of implementing a part of the system, either in software or in hardware, can produce incorrect or unsatisfactory results. Co-design methodologies have been developed to aid the development of such systems. The partitioning phase is one of the tasks carried out by a co-design methodology. It divides the original system into components taking in account software or hardware implementation. This work presents a model to carry out data dependency analysis, which is one of the aspects considered for the partitioning algorithm of the PISH codesign methodology.

The article presents two approaches for computing the number of functional units in a hardware/software codesign context. The proposed hardware/software codesign framework uses the Petri net as a common formalism for performing quantitative and qualitative analysis. The use of the Petri net as an intermediate format allows us to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. The paper is devoted to describing the algorithms for functional unit estimation. The work also proposes a method of extending the Petri net model in order to take into account causal constraints provided by the designers. However, an overview of the general hardware/software codesign method is also presented.

This work presents a method of hardware/software partitioning considering multiple software components. The proposed method uses Petri nets as a common formalism to perform quantitative and qualitative analysis. The use of Petri net permits one to use a specification nondependent partitioning method. As an intermediate format Petri net allows one to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper highlights methods of computing load balance, precedence relation degree and communication cost of behavioral description in order to perform the initial allocation along with partitioning. This paper is devoted to describing the initial allocation algorithm, although an overview of the general partitioning method is also presented.

In this paper we present the development and implementation of an intravenous infusion controller system based on FPGA's. The system receives information of an infusion drop sensor and controls the drop flow by giving the direction and number of steps of a stepper motor, which compress the drip-feed hose. The system consists of a mixed implementation of software and hardware. The software was implemented in C++ and the hardware was implemented by using FPGA's.

This work presents a timed constraints capture method that uses Timed Petri nets for systems written in OCCAM in the context of Hardware/Software partitioning. We present a method for translation of occam programs into timed Petri-nets as well as a time analysis method in the context of hardware/software partitioning. The time analysis allows the capture of the execution time of processes and sub-process, which are used in the hardware/software partitioning process.