International audience

International audience

Soft errors and power dissipation emerge as critical challenges in developing high-reliability and cost-sensitive embedded systems. To address these issues, the magnetic tunnel junction (MTJ) is considered a promising solution due to its nonvolatility and its compatibility with traditional CMOS manufacturing processes. In this work, we propose a novel nonvolatile (NV) latch consisting of inverters and MTJs, namely, NVLIM, which provides nonvolatility and robust partial tolerance against triple-node-upsets (TNUs) at low cost. NVLIM integrates a TNU-tolerant block based on CMOS with a backup-restore block using MTJs. Simulation results incorporating process, voltage, and temperature (PVT) variations, bias temperature instability (BTI) impact, and Monte Carlo simulations demonstrate the balanced performance in terms of nonvolatility, robust partial TNU tolerance, and comprehensive overhead of the proposed latch.

The Cell-Aware (CA) methodology has become essential to detect and diagnose manufacturing intra-cell defects in modern semiconductor technologies. It characterizes standard cells by creating a defect-detection matrix, which serves as a reference that maps stimuli to the specific defects they can detect. Its limitation is that CA approach needs a number of time-consuming analog simulations to create the matrix. In [1] a graph-based methodology able to reduce the number of simulations to perform, called Transistor Undetectable Defect eLiminator (TrUnDeL), was presented. TrUnDeL can identify undetectable stimulus/defect pairs that are then excluded from the analog simulations. However, its use is limited to combinational cells and does not offer any guidance on handling sequential cells, which are usually the most complex cells. In this paper we present a new version of TrUnDeL that supports sequential cells analysis. Experiments conducted on sequential cells from two standard cell industrial libraries demonstrate that the CA generation time is reduced by 30% without compromising accuracy.

This paper presents a FeFET-based non-volatile and single-event upset (SEU) recoverable latch, namely NVSRLO, which does not require any extra control signals. Simulation results show that the proposed latch provides non-volatility and SEU-recovery with optimized overhead. Compared with existing non-volatile latches, NVSRLO significantly reduces delay, power, and delay-power-area product at the cost of area.

The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Testing advanced memories is essential for ensuring modern System-on-Chip quality. As transistor size continues to shrink, the probability of the occurrence of manufacturing defects increases, making conventional functional testing of SRAMs inadequate for achieving required Defect Parts per Million (DPPM). To address this issue, a novel structural testing approach using the Cell-Aware (CA) test methodology has been proposed in [1]. With this methodology, structural test patterns are obtained through an Automatic Test Pattern Generator (ATPG) by exploiting analog CA models (i.e., based on exhaustive analog simulations) for SRAM primary blocks. However, the generation of CA models through analog simulations is time-consuming and technology dependent. A methodology, namely TrUnDeL proposed in [2], is used to accelerate the CA model generation, combining a switch-level graph-based solution and analog simulations. In this work, we propose an adaptation of TrUnDeL to generate the CA models, using only the switch-level graph-based simulations. TrUnDeL CA models are then used by the ATPG to generate structural test patterns. Through a validation flow, we demonstrate that the aforementioned patterns, generated without running any analog simulations, achieve nearly the same fault coverage as the test patterns generated using exhaustive analog simulations on an SRAM case study. The time required to generate CA models is drastically reduced with TrUnDeL, from 1 hour to 15 seconds for the considered case study.

Modern integrated circuits such as System-On-Chip (SOC) require a large amount of memory. The integration density of these memories is based on the extreme miniaturization of the technological nodes. However, the miniaturization process contributes to an increase in the occurrence of physical defects. In order to verify the quality of memories, new test methods, based on structural testing, have been proposed recently. However, these methods rely on a digital test environment and require an accurate modeling of the memory. This work proposes a digital SRAM modeling compatible with digital simulation and test environments. The digital SRAM modeling presented in this paper is functionally equivalent to an analog SRAM model (i.e., memorization, Write and Read operations). The memorization capability of the model enables it to consider the data-background of the memory array during testing, facilitating the evaluation of complex test sequences, such as March algorithms, in covering structural fault models (i.e., Cell-Aware fault models).

As semiconductor technology advances, radiative-particle-induced soft errors and power consumption are becoming major concerns for digital circuits in aerospace applications. Radiation hardening by design and magnetic tunnel junctions (MTJs) are widely employed to address these concerns. In this paper, a novel latch, called TNURML, that can completely recover from triple-node upsets (TNUs), is proposed. The embedded MTJs provide non-volatility and are compatible with traditional CMOS processes. The TNURML employs a TNU-recovery module as well as a pair of MTJs for backup and recovery operations. Extensive simulations demonstrate the excellent TNU-recovery capability and non-volatility of the TNURML latch at the cost of slightly increased area overhead. The proposed TNURML latch reduces 43.63% of delay and 48.23% of power on average when compared to the state-of-the-art latches.

Building an interpretable fault detection and diagnostic model based on few-shot circuit samples and prior information about circuit structures is of significant importance. To fill these gaps, we propose a graph-based multitask transfer learning (TL) method for fault detection and diagnosis of circuits under few-shot conditions. First, in order to model the interconnections of nodes in a circuit, the sample data is organized into a graph structure, and a semi-supervised graph-based structural feature fusion method is proposed. The proposed method can accept graph-structured data and process the data using feature fusion methods. Second, to improve the model performance under few-shot conditions, two TL mechanisms are proposed for the topological structure characteristics of analog circuits as well as circuit signal characteristics. Finally, through a parameter-shared strategy, we propose a task transfer-based fault diagnosis approach. Experimental results on three different circuits show that the proposed method has the best diagnostic accuracy compared to typical detection and diagnosis schemes.

With the rapid advancement of semiconductor technologies, latches become increasingly sensitive to soft errors, especially triple node upsets (TNUs), in harsh radiation environments. In this article, we first propose a high-performance and area-efficient latch, namely, HALTRAV, featuring complete TNU-recovery. The storage portion of HALTRAV consists of 28 interlocked source-drain cross-coupled inverters (SCIs) for complete TNU-recovery with area efficiency and low delay. To mitigate the issue that node-upset-recovery verifications for existing latches highly relies on electronic design automation tools, we further propose an algorithm-based verification method that can automatically verify the node-upset-recovery of latches, which greatly simplifies the reliability-verification flow. Simulation results demonstrate the TNU-recovery of HALTRAV and also show that HALTRAV achieves 40.38%, 8.17%, and 31.89% reduction in delay, area, and delay-power–area product (DPAP) on average, respectively; however; it is at the cost of power as compared to typical latches that are TNU-recoverable. Comparison results also demonstrate the moderate sensitivity of HALTRAV to the impacts of the process, voltage, and temperature (PVT) variations.

Testing memory circuits is crucial for ensuring the quality and reliability of system-on-chip (SoC) designs, especially as shrinking technology nodes increase susceptibility to nanometer-scale defects. This article introduces an enhanced methodology for memory testing, leveraging the cell-aware (CA) test concept. Building on prior work for SRAM array testing (Xhafa et al., 2023), we extend the CA methodology to include periphery testing by generating, for the first time, CA models for each memory input–output (I/O) element, covering key components, such as address decoders, write drivers, and sense amplifiers. We present results from testing these periphery components using the CA methodology. Additionally, we compare existing SRAM testing techniques with our CA methodology for the decoder and I/O circuitry. To ensure a fair comparison, we selected minimal March tests designed to detect functional faults in peripheral circuits, aligning with the fault models targeted by our approach. A quantitative analysis of fault coverage demonstrates the effectiveness of our methodology compared to March algorithms, particularly in terms of test complexity.

This article presents radiation-hardened flip-flop (FF) designs capable of tolerating soft errors, e.g., single-node upsets (SNUs), double-node upsets (DNUs) and multiple-node upsets (MNUs). First, a 2-input FF and a 3-input FF are proposed as the baseline FFs that not only, respectively, tolerate SNUs and DNUs but also exhibit cost efficiency in terms of delay, power, and area. Through adding two stages of c-elements, a 4-input FF and a 5-input FF are proposed as the baseline FFs as well. Utilizing the structural characteristics of these FFs, an$N-1$input FF and an N input FF are proposed as the extended FFs capable of tolerating more node upsets. Moreover, a highly efficient algorithm for verifying MNU-tolerance of these FFs is proposed. Algorithm and HSPICE-tool-based verification results both demonstrate the MNU-tolerance for the proposed FFs with more inputs.

With the continuous advancement of CMOS technologies, soft errors, such as single-node upset (SNU) and double-node upset (DNU), caused by radiation in nanoscale integrated circuits, are becoming increasingly prominent. Meanwhile, transistor aging mitigation is indispensable for long-term robustness enhancement. First, to reduce the impact of radiation on circuits, we propose a novel DNU-recovery latch with low cost, namely, DURLC, only consisting of four dual-input C-elements (CEs) and four clock-gated input-split inverters for the storage of values. Second, we propose a DNU-recovery latch with moderate cost, namely, DURMC, based on seven CEs and four inverters, for convenience to optimize the latch to alleviate aging. The proposed DNU-recovery latch with mitigated aging is called DURMA. The latch employs a high-speed path to reduce delay without sacrificing performance when mitigating aging issues. Finally, we propose an algorithm-based verification method to validate the DNU recovery of the proposed latches. The simulation results show that, compared with the state-of-the-art robust latches, the proposed latches have the advantages of DNU recovery with moderate and even low cost, and meanwhile, aging is effectively mitigated for the DURMA latch.

Spintronic devices, such as magnetic tunnel junctions (MTJs), are promising for space applications due to their radiation hardness and nonvolatility. However, as semiconductor technology advances, CMOS peripheral circuits are becoming vulnerable to double node upset (DNU) as well as triple node upset (TNU). This brief proposes two nonvolatile and robust latch designs primarily composed of MTJs and C-elements (CEs). Both designs offer nonvolatility and self-recovery from multiple-node upsets. Simulation results demonstrate that the proposed latches provide nonvolatility and complete protection against multiple-node upsets with balanced overhead.

In nanoscale CMOS technology, harsh radiations in the environment can now easily cause soft errors, e.g., single-event transients (SETs) and triple node upsets (TNUs), severely affecting the reliability of space applications. In this article, TNUs tolerant and SET-pulses filtered latch (TUTPFL) with low power is proposed, which comprises from four input-stage C-elements (CEs), four inverters, and three output-stage CEs. The CEs’ delay differential enables the TUTPFL latch to effectively filter SET-pulse, while the CEs’ multilevel error-interception property enables the TUTPFL latch to tolerate any possible TNU. The results of HSPICE-based simulations and FPGA-based emulations demonstrate the TNU tolerance and SET filterability of the TUTPFL latch. Meanwhile, compared to the alternative radiation-hardened latches, the TUTPFL latch reduces power dissipation by roughly 20.43% on average.

The shift towards data-centric computing paradigms has given rise to new architectural approaches aimed at minimizing data movement and enhancing computational efficiency. In this context, In-Memory Computing (IMC) architectures have gained prominence for their ability to perform processing tasks within the memory array, reducing the recourse to data transfers. However, the susceptibility of these new paradigms to manufacturing defects poses a critical test challenge. This paper presents a novel March-like test algorithm for 8T SRAM-based IMC architectures, addressing the imperative need for comprehensive read port related defect coverage. The proposed algorithm achieves complete coverage of potential read port defects while maintaining the level of complexity equivalent to existing state-of-the-art test solutions.

Modern powerful CMOS chips are usually highly integrated and implemented with aggressively shrunk technology nodes. In radiation environment, under charge-sharing mechanism, one particle striking can simultaneously impact multiple nodes causing double-node-upsets (DNUs) and triple-node-upsets (TNUs). In this paper, we propose an Interlocked Dual-circle Latch Design, namely IDLD, with low cost and TNU recovery for aerospace applications. IDLD consists of four transmission gates and twelve 2-input C-elements (CEs) implemented in 22nm CMOS process. Simulation results demonstrate the complete TNU recovery as well as cost-effectiveness for the proposed IDLD latch.

The reduction in transistor size in modern Integrated Circuits (ICs) has led to an increase in manufacturing defects within standard cells, also known as intra-cell defects. Detecting these defects and localizing them through diagnosis is crucial for achieving a fast yield ramp-up and ensuring a low test escape rate. Traditional fault models, such as stuckat and transition, do not effectively represent intra-cell defects. To address this issue, the Cell-Aware (CA) methodology was introduced. However, this technique involves time-consuming analog SPICE simulations to characterize standard cells. This paper presents a methodology, called Transistor Undetectable Defect eLiminator (TrUnDeL), based on graph theory to speed up the CA model generation process. Our methodology identifies undetectable defects for each stimulus applied at the inputs of the cell, which are then excluded from the analog simulations. We applied TrUnDeL to two libraries from STMicroelectronics (P28 and C28) to identify the undetectable stimulus/defect pairs, so that analog simulations are performed only on the remaining pairs. As a result, the CA model generation process time is reduced by a factor of 3. Finally, we applied TrUnDeL to a SRAM bitcell case study and demonstrated that the obtained results are consistent with its existing CA model.

Nonvolatile memories are widely used in emerging energy-harvesting Internet-of-Things (IoT) applications, and nonvolatile memories constructed from FeFET devices hold great promise. This paper presents a nonvolatile and single-event-upset (SEU)-recoverable latch based on FeFET and CMOS for energyharvesting devices. The latch uses n-type FeFET devices to provide nonvolatility without any additional control signals. Moreover, since the soft error problem has become increasingly severe, radiation hardening by design gains a great attention as a promising approach to mitigate the reliability issue. The latch uses feedback interlocked loops with n-type FeFETs and C-elements, enabling it to provide nonvolatility and SEU-recovery simultaneously. Simulation results with Candence Virtuoso verifies that the proposed latch design has correct functioning with excellent performance compared to the state-of-the-art designs.

As modern Integrated Circuits (ICs) feature ever-smaller transistors, the prevalence of manufacturing defects within standard cells (intra-cell defects) has increased. Detecting and localizing these defects is crucial to guarantee a fast yield ramp-up and to maintain a low-test escape rate. Unfortunately, traditional fault models such as stuck-at and transition fail to adequately represent intra-cell defects. Cell-Aware (CA) was introduced to tackle this problem, but it requires time-consuming analog SPICE simulations for standard cell characterization. To speed-up the CA model generation process, this paper presents a methodology based on graph theory called Transistor Undetectable Defect Eliminator (TrUnDeL). This methodology identifies undetectable defects for each stimulus applied to the inputs of the cell, subsequently excluding them from the analog simulations to perform. TrUnDeL uses rule-based and propagation-based techniques and was trialed on combinational and sequential cells of two 28nm libraries from STMicroelectronics (P28 and C28) to identify the undetectable stimulus/defect pairs, so that analog simulations are performed only on the remaining pairs. As a result, the CA model generation process time was reduced by a factor of 3 compared to a standard SPICE-based generation process.

In advanced CMOS technologies, integrated circuits are sensitive to multiple-node-upsets (MNUs) induced in harsh radiation environments. The existing verification of the reliability of latches highly relies on electronic design automation (EDA) tools considering complex error-injection scenarios. In this paper, we propose a novel latch, namely MURLAV, protected against quadruple node-upsets (QNUs) induced in harsh radiation environments, as well as an algorithmic error-recovery verification method. The latch provides complete recovery from all QNUs with a formed redundant structure. The algorithm can simplify the verification process and demonstrate the QNU recovery for the proposed MURLAV latch. Simulation results demonstrate that the proposed latch can recover from any QNU and that it has lower area and delay overhead. Compared with existing latches of the same type, the proposed MURLAV latch achieves an overhead reduction of 34% in silicon area and 15% in delay on average at the cost of moderate power consumption.

As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) are widely used to address these concerns. MTJs are nonvolatile (NV) and compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant and NV latch, i.e., M-TPDICE-V2, providing high reliability. In addition, we further propose an advanced latch, namely, M-8C, that is able to completely recover from single-node upsets (SNUs) and DNUs. M-8C uses a DNU recovery module and a backup and restore module based on a pair of MTJs. Furthermore, we propose a universal backup and restore module suitable for any latch providing nonvolatility. We simulate the proposed latches using the Synopsys HSPICE tool with a 45-nm CMOS process model. Simulation results confirm the superior capabilities of our proposed M-TPDICE-V2 and M-8C latches. M-TPDICE-V2 exhibits strong SNU and DNU tolerance and nonvolatility, while the M-8C latch provides complete DNU recovery capabilities.

With the advancement of CMOS technologies, circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). To effectively provide nonvolatility as well as tolerance against DNUs caused by radiation, this paper proposes a nonvolatile and DNU resilient latch that mainly comprises two magnetic tunnel junction (MTJ), two inverters and eight C-elements. Since two MTJs are used and all internal nodes are interlocked, the latch can provide nonvolatility and recovery from all possible DNUs. Simulation results demonstrate the nonvolatility, DNU recovery and high performance of the proposed latch.

The adoption of In-Memory Computing (IMC) architectures is one of the promising approaches to efficiently solve the Von Neumann bottleneck problem. In addition to arithmetic operations, IMC architectures aim at integrating additional logic operations directly in the memory array or/and at the periphery for saving time and power consumption. In this paper, a comprehensive model of a 128x128 bitcell array based on a 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive-open defects injected in the read port. A hierarchical analysis including a detailed study of each defect was performed in order to determine their impact both in memory and computing modes, both locally on the defective bitcell and globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-open defects.

The shrinking of technology nodes has led to high-density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This Ph.D. thesis aims to introduce a novel approach for advanced and emerging memory testing that relies on the Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs).

The shrinking of technology nodes has led to high density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This paper presents a novel approach for memory testing which relies on Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs). Consequently, using CA methodology converts memory testing from functional to structural testing. In this work, the preliminary flow of the CA-based memory testing methodology is presented. The generation of the CA model for the SRAM bit cell has been demonstrated as a case study. The generated CA model and the structural representation of the memory are used by the ATPG to test the bit cell in the presence of short and open defects. The generated test patterns are able to detect both static and dynamic faults in the bit cell with a test coverage of 100%.

Many applications have an inherent tolerance for insignificant inaccuracies. Full adders are key arithmetic functions for many error-tolerant applications. Approximate full adders are considered an efficient technique to trade off energy relative to performance and accuracy. In this paper, we propose four approximate full adders with low overhead. The proposed and the existing approximate full adders are classified into two groups according to their error distances. Simulation results show that, compared with the existing approximate full adders, in the first group, the proposed ones can reduce power-area-delay product (PADP) by 61.83%, power by 54.15%, area by 44.67%, and delay by 22.78%on average; in the second group, the proposed ones can reduce PADP by 97.01%, power by 93.43%, area by 24.98%, and delay by 36.14% on average.

For high-speed operations, low power consumption and small silicon area, transistors are being scaled aggressively. Meanwhile, circuit reliability is facing greater challenges in advanced technologies. In this paper, a highly reliable and low-power SRAM with double-node-upset (DNU) recovery, namely HRLP16T, is proposed for safety-critical fields. HRLP16T can recover from single-node-upset (SNU) at all the sensitive nodes, and it has eight node pairs recoverable from DNUs. Simulation results demonstrate its advantages in terms of delay and power consumption over typical existing SRAM cell designs.

With the rapid advancement of semiconductor technologies, integrated circuits, especially storage elements (e.g., latches) have become increasingly vulnerable to soft errors. In order to effectively tolerate double-node-upsets (DNUs) caused by radiation and reduce the power and area of latches, this paper proposes a DNU self-recoverable latch with low overhead in terms of power and area. The proposed latch mainly comprises seven 2-input C-elements and two inverters to achieve DNU self-recovery. Simulation results show that the proposed latch can recover from all possible DNUs and that it can reduce delay by 45.7%, power by 29.1%, area by 65.9%, and area-power-delay-product by 87.4%, on average, compared to typical existing DNU self-recoverable latches.

As CMOS processes continue to shrink, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiation. To tolerate MNU, a novel quadruple-node-upset (QNU) self-recoverable latch is proposed in this paper. The proposed latch is mainly constructed from six blocks of three-level C-elements (TLCEs) and six inverters. With the mutual feedback of the various TLCEs, the proposed latch can recover from any QNU. Furthermore, due to the clock gating methodology and a high-speed transmission path, the proposed latch has lower overhead in terms of power dissipation and transmission delay. Simulation results show that the proposed latch achieves high reliability with moderate overhead compared to typical existing latches.

The optical test of CMOS Image Sensors (CIS) represents a major part of the overall test time. It consists in applying two-dimensional image processing algorithms on the output images of the CIS under test. In [1], we demonstrated that it is possible to embed 50% of these algorithms in the CIS by using a dedicated Built-In Self-Test (BIST) engine without impacting the defect coverage and at a negligible area cost (approximately 0.25% of the total sensor area). The use of a BIST solution reduces the optical test time by roughly 30% when compared to the optical algorithms traditionally applied by using an Automatic Test Equipment (ATE). However, the effectiveness of this approach is limited by the fact that some global subtle defects cannot be detected. This is a real problem as these defects can seriously impact the output image quality. To overcome this drawback, this paper presents a new BIST solution, called Predictor BIST (PRED BIST) based on a global overview of the image under test. The novelty of this approach lies in the use of an arithmetic method to build an ideal (i.e., predicted) image from wisely selected samples extracted from each output image of the CIS under test. The process of building an ideal image is repeated for all images to be checked for the CIS under test. By comparing each output image to the ideal image, it is then possible to classify good and bad images. Moreover, PRED BIST is an all-in-one test solution that allows to fully replace the optical test done today with an ATE by an embedded test solution. This is an important and unique feature of PRED BIST. Two databases were used to validate this new BIST solution. The first one is an extension of the monocolor database of 27,600 images used in [2] and the second one contains 81,840 images from a RGB sensor. Validation shows that compared to conventional ATE-based test, a correlation of 99.90% and 99.40% respectively is achieved regarding the classification between good and bad images of two considered databases. Moreover, the global defects missed by the test solution in [1] are always found by PRED BIST. This new test solution results in a reduction of up to 95% of the optical test time.

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

With technology scaling down, the vulnerability of circuits to radiation and the increase of static power have become severe concerns. Spintronic devices such as magnetic tunnel junction (MTJ) have been developed to cope with many concerns, among which reliability concerns [1]. Spintronic devices have attractive properties, such as non-volatility and compatibility with conventional CMOS fabrication process. Based on an advanced triple-path dual-interlocked-storage-cell (TPDICE) and MTJs, this paper proposes a radiation-hardened non-volatile magnetic latch, namely M-TPDICE, that can completely tolerate single-node upsets (SNUs) and double-node upsets (DNUs). Simulations of the proposed latch with the HSPICE tool with a 45 nm CMOS technology model have demonstrated the effectiveness of the proposed latch.

As the CMOS technology is continuously scaling down, nano-scale integrated circuits are becoming susceptible to harsh-radiation induced soft errors, such as double-node upsets (DNUs) and triple-node upsets (TNUs). This paper presents a shuttle C-elements based low-cost and robust latch (namely SCLCRL) that can recover from any TNU in harsh radiation environments. The latch comprises seven primary storage nodes and seven secondary storage nodes. Each pair of primary nodes feeds a secondary node through one C-element (CE) and each pair of secondary nodes feeds a primary node through another CE, forming redundant feedback loops to robustly retain values. Simulation results validate all key TNUs' recoverability features of the proposed latch. Simulation results also demonstrate that the proposed SCLCRL latch can approximately save 29% silicon area and 47% D-Q delay on average at the cost of moderate power, compared with the state-of-the-art TNU-recoverable reference latches of the same-type.

In-field test of integrated circuits using Self-Test Libraries (STLs) is a widely used technique specifically suited to guarantee the processor’s correct behavior during the operative lifetime, as mandated by functional safety standards such as ISO26262. Developing STLs for stuck-at faults requires significant manual efforts from test engineers, and targeting delay faults is even more challenging. In order to support this process, in this paper we propose a method to automate the creation of STLs targeting delay faults starting from existing STLs targeting stuck-at faults. The method is based first on identifying excited but not-observed transition delay faults and then adding suitable instructions able to detect them. Experimental results on a RISC-V processor show that the method can systematically detect a significant percentage of the target faults with reasonable computational effort and test code size increase.

This paper demonstrates the generalization of a novel test solution embedded inside CMOS Image Sensors (CIS) to classify PASS/FAIL sensors during the test production phase. In [1], a Built-In Self-Test (BIST) solution was proposed to reduce the test time of a CIS, which can represent up to 30% of the final product cost. The major part of the test is dedicated to optical (i.e. image processsing) algorithms performed on the output images from the sensor under test with an Automatic Test Equipment (ATE). The BIST solution reuses these optical algorithms by simplifying and embedding them inside the sensor, to avoid a large amount of data storage and to limit the optical test time. First results on 4,800 output images from a package of sensors have shown a 99.95% correlation between results gathered from an ATE and those achieved with the proposed BIST, with a saving of approximately 30% in optical test time and a negligible area footprint. In this paper, to verify the effectiveness of the BIST solution on a wider set of different CIS (i.e., architecture, size and technology), we experimented the solution on a new database of 28,000 output images from a package of different sensors compared to the first package used in [1]. The BIST parameters have been configured to fit with the new type of sensors and results show a 99.64% correlation, which demonstrates the possible systematic implementation of the proposed BIST solution inside all CIS irrespective of their architecture and technology.

This paper proposes a novel sextuple cross-coupled dual-interlocked-storage-cell (DICE) based double-node-upset (DNU) recoverable and low-delay flip-flop (FF), namely SCDRL-FF, for aerospace applications. The SCDRL-FF mainly consists of sextuple cross-coupled DICEs controlled by clock-gating. The use of clock-gating based DICEs significantly reduces the CLK-Q transmission delay of the SCDRL-FF. Through the redundant and interlocked clock-gating based DICEs, the SCDRL-FF can provide complete DNU recoverability. Simulation results demonstrate the DNU recoverability of the SCDRL-FF and a 65% delay reduction on average compared with the state-of-the-art hardened FFs. The low delay overhead makes the proposed SCDRL-FF effectively applicable to high-performance applications and the DNU recoverability makes the proposed SCDRL-FF also suitable for aerospace applications.

Aggressive scaling of CMOS technologies requires to pay attention to the reliability issues of circuits. This paper presents two highly reliable RHBD 10T and 12T SRAM cells, which can protect against single-node upsets (SNUs) and double-node upsets (DNUs). The 10T cell mainly consists of two cross-coupled input-split inverters and the cell can robustly keep stored values through a feedback mechanism among its internal nodes. It also has a low cost in terms of area and power consumption, since it uses only a few transistors. Based on the 10T cell, a 12T cell is proposed that uses four parallel access transistors. The 12T cell has a reduced read/write access time with the same soft error tolerance when compared to the 10T cell. Simulation results demonstrate that the proposed cells can recover from SNUs and a part of DNUs. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed 10T cell can save 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input C-elements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively.

With the aggressive reduction of CMOS transistor feature sizes, the soft error rate of nano-scale integrated circuits increases exponentially. In this paper, we propose a novel cost-optimized and robust latch, namely CRLHQ, hardened against quadruple-node-upsets (QNUs) for nanoscale CMOS technologies. The latch mainly comprises a 5×5 matrix based on interlocked source-drain cross-coupled inverters to robustly store logic values. Owing to the redundant constructed feedback loops, the latch can recover from all possible QNUs. Simulation results demonstrate all key QNUs' recovery of the proposed CRLHQ latch. Simulation results also show that the proposed latch can approximately reduce the D-Q delay by 44.3%, the silicon area by 7.3% and the delay-area-power product (DAPP) by 14.2%, compared with the state-of-the-art same-type reference latches that can recover from any QNU.

As the semiconductor industry continues to shrink the transistor feature size, new fault models need to be invented and deployed to ensure manufacturing test and diagnostic of the highest quality. The Cell-Aware (CA) test and diagnosis methodology targets the detection of defects inside standard (std) cells, at the transistor level. While becoming an industry standard, the CA methodology, has a large and costly deployment overhead, involving numerous analog simulations. In [1], we presented an innovative flow using Machine-Learning (ML) to reduce the CA test method runtime and ease its adoption for industrial usage. Experiments using different technology nodes demonstrated an over 99% runtime reduction for 80% of combinational cells. In this paper, new elements are presented to more widely take advantage of the ML flow for CA characterization. This includes a new decision algorithm, leveraging ML techniques to decide whether the CA characterization of a new std cell should be ML-based or simulation-based, thus allowing to decrease the CA characterization runtime while maintaining high quality CA models for all cells. Experimental results demonstrate the high performance of the new decision algorithm. The fault coverage on real cell-internal defects of ATPG patterns using ML predicted CA data proves that our predicted CA data can accurately replace those obtained by running extensive analog simulations, thus proving the effectiveness and pertinence of the proposed methodology.

In space, the impact of radiative particles, such as neutrons and heavy ions, can change the node states of a flip-flop, thus resulting in loss of data. In this paper, a Highly reliable and Low power Radiation-hardened-by-design (RHBD) Flip-Flop cell, namely HLRFF, completely hardened against double-node-upsets (DNUs), is proposed for aerospace applications. The HLRFF is a master-slave structure. The master latch is mainly constructed from two 2-input C-elements (CEs) and one 2-input clock-gating based CE, while the slave latch has an additional keeper at the output stage. The verification results demonstrate that the proposed HLRFF is completely DNU-tolerant. Furthermore, compared to the state-of-the-art radiation-hardened FF cells, the proposed HLRFF can reduce power consumption by approximately 69%. However, only the proposed HLRFF is not only completely DNU-tolerant but also insensitive to high-impedance-state.

Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates the All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61%. With ± 20% supply voltage and 5°C to 105°C temperature variations, the All-Spin PUF shows a strong resiliency. In comparison with state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of the All-Spin PUF against emerging modeling attacks is verified as well.

Cell-aware model generation refers to the process of characterizing cell-internal defects, a key step to ensure high test and diagnosis quality. The main limitation of this process is the generation effort, which is costly in terms of run time, SPICE simulator license usage and flow complexity. in this work, a methodology that does not use any electrical defect simulation is developed to predict the response of a cell-internal defect once it is injected in a standard cell. More widely, the aim is to use existing cell-aware models from various standard cell libraries and technologies to predict cell-aware models for new standard cells independently of the technology. A Random Forest classification algorithm is used for prediction. Experiments on several cell libraries using different technologies demonstrate the accuracy and performance of the method. The paper concludes by the presentation of a new hybrid CA model generation flow.

The paper addresses some of the opportunities and challenges related to test and reliability of three major emerging computing paradigms; i.e., Quantum Computing, Computing engines based on Deep Neural Networks for AI, and Approximate Computing (AxC). We present a quantum accelerator showing that it can be done even without the presence of very good qubits. Then, we present Dependability for Artificial Intelligence (AI) oriented Hardware. Indeed, AI applications shown relevant resilience properties to faults, meaning that the testing strongly depends on the application behavior rather than on the hardware structure. We will cover AI hardware design issues due to manufacturing defects, aging faults, and soft errors. Finally, We present the use of AxC to reduce the cost of hardening a digital circuit without impacting its reliability. In other words how to go beyond usual modular redundancy scheme.

In this paper, a new XOR gate is discussed in quantum-dot cellular automata (QCA). The proposed gate is a single layer structure with no crossovers, and has been designed with redundant cells to increase the amplitude of the output signal and to improve the fault tolerance and reliability of the circuit. Based on the performance comparison, the investigated XOR gate has very high fault tolerance to single-cell addition and single-cell omission defects, thereby making them suitable candidates for designing reliable QCA based digital circuits.

Soft error is one of the major reliability issue with technology scaling. In this work, we propose a radiation hardened voltage bootstrapped schmitt trigger (VB-ST) latch. To evaluate the circuit radiation resilience, we calculated the critical charge under the PVT variations at the most sensitive node and observed that the proposed latch has the highest critical charge and the lowest soft error rate ratio when compared to existing latches. We analyzed the impact of process variations on our design and observed that the VB-ST latch has 0.42x less critical voltage variability as compared to ST latch. Further, dynamic power and propagation delay are examined for various supply voltages, and we observed that the VB-ST latch has the lowest power consumption and delay propagation when compared to the other considered latches. For the validation of the proposed latch, a charge to power-delay-area product ratio (QPAR) is calculated and we clearly observed that the proposed VB-ST based latch significantly outperforms the performance of existing designs.

This paper proposes a 4-node-upset (4NU) recoverable and high-impedance-state (HIS) insensitive latch design, namely QRHIL, for highly robust computing in harsh radiation environments. The latch mainly comprises a 5×5 looped C-element matrix to store values and provide complete 4NU recovery. Owing to the multiple-level error-interception of the 5×5 C-element matrix, the latch can recover from all possible 4NUs; thus, the latch is insensitive to HIS. Simulation results demonstrate the 4NU-recovery of the proposed latch. The results also show that the latch can approximately save 46% D-Q delay and 46% CLK-Q delay owing to the use of a high-speed D-Q path and clock-gating, compared with the state-of-the-art 3NU-recoverable latch (TNURL) that is not 4NU-recoverable.

Testing digital integrated circuits is generally done using Design-for-Testability (DfT) solutions. Such solutions, however, introduce non-negligible area and timing overheads that can be overcome by adopting functional solutions. In particular, functional test of integrated circuits plays a key role when guaranteeing the device's safety is required during the operative lifetime (in-field test), as required by standards like ISO26262. This can be achieved via the execution of a Self-Test Library (STL) by the device under test (DUT). Nevertheless, developing such test programs requires a significant manual effort, and can be non-trivial when dealing with complex modules. This paper moves the first step in defining a generic and systematic methodology to improve transition delay faults' observability of existing STLs. To do so, we analyze previously devised STLs in order to highlight specific points within test programs to be improved, leading to an increase in the final fault coverage.

Until recently, Approximate Computing (AxC) was considered to be a trend topic mainly for resilient applications. Its use aimed at reducing area and power consumption of Integrated Circuits (ICs) at the cost of a reduced accuracy. Beside, AxC-based fault-tolerance has also emerged recently to save area et power consumption w.r.t. conventional fault-tolerance at the cost of a reduced reliability level. Therefore, approximate fault-tolerance is restricted to non-critical applications. In a previous work, a Quadruple Approximate Modular Redundancy (QAMR) scheme, based on using four approximate circuit copies, was proposed. In a single fault scenario, it provides the same reliability level as Triple Modular Redundancy (TMR). Moreover, QAMR allows reducing area and power consumption costs w.r.t. TMR in many cases. In this paper, we study the occurrence of multiple faults, and compare the QAMR and TMR behaviors. Experimental results highlight the TMR overprovision (i.e. it provides more redundancy than necessary) and show how the QAMR approach can reduce it. Moreover, a thorough analysis of the results shows that a high tolerance to multiple faults is associated to a large circuit area and to a lower percentage of logic shared among different fan-in cones of the circuit outputs.

This paper presents a novel test solution directly embedded inside CMOS Image Sensors (CIS) to sort out PASS and FAIL dies during production test. The solution aims at reducing test time, which can represent up to 30% of the final product cost. By simplifying the way optical tests are usually applied with an ATE, the proposed Built-In Self-Test (BIST) solution overcomes the drawbacks of long test time and huge amount of test data storage. We experimented our solution by considering that roughly half of the tests usually performed with an ATE can be embedded and applied using the proposed fast and low cost BIST engine. Results obtained on more than 2,400 sensors have shown that our solution reduces test time by about 30% without impacting the defect coverage. The area cost of our solution is about 1% of the digital part of the sensor, i.e., approximately 0.25% of the total sensor area. The proposed embedded CIS test solution outperforms existing solutions in terms of area overhead and test time saving, thus encouraging its future implementation in an industrial production flow.

Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed so far for various MRAM technologies. The last part of this article gives some perspectives on this hot topic.

As device integration density increases exponentially as predicted by Moore's law, power consumption becomes a bottleneck for system scaling where leakage power of on-chip cache occupies a large fraction of the total power budget. Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate to replace static random access memory (SRAM) as an on-chip last level cache (LLC) due to its ultralow leakage power, high integration density, and nonvolatility. Moreover, with the prevalence of edge computing and Internet-of-Things (IoT) applications, it can be beneficial to build a total nonvolatile cache hierarchy, including the L1 cache. However, building an L1 cache with STT-MRAM still faces severe challenges particularly because reducing its relatively high write latency by increasing write voltage can accelerate oxide breakdown of the MTJ device and threaten the L1 cache lifetime significantly due to intensive accesses. In our previous work, we proposed a dynamic overwriting voltage adjustment (DOVA) technique to deal with this challenge. In this article, we improve this technique by a DOVA promotion (DOVA PRO) technique for the STT-MRAM L1 cache, considering the cache write endurance and performance simultaneously. A high write voltage is used for performance-critical cache lines, while a low write voltage is used for other cache lines to approach an optimal tradeoff between reliability and performance. Experimental results show that the proposed technique DOVA PRO can improve cache performance by 23.5%, on average, compared to the DOVA technique. In the meantime, the average degradation of cache lifetime remains almost unchanged compared with the DOVA technique on average. Furthermore, DOVA PRO can support flexible configurations to achieve various optimization targets, such as higher performance or a longer lifetime.

Aerospace applications are attractive candidates to embed artificial neural networks despite their excellent parallel processing capability and reduced energy consumption. Nonetheless, the long-term exposure to incidence levels of ionizing radiation may degrade their physical components reducing, therefore, their reliability and expected lifetime. Thus, it is mandatory to face the challenge of enhancing the radiation hardening characteristics of a neural circuit before operating in harsh environments. A possible solution to substantially reduce long-term spurious effects caused by ionizing radiation [referred to as total ionizing dose (TID)] is to change the conventional rectangular MOS gate geometry to a nonstandard topology referred to as an enclosed layout transistor (ELT). In the context of hardening a complete neuron circuit against TID effects, together with the well-established ELT paradigm, it is possible to exploit the inclusion of other hardened devices, for instance, the memory element. In this sense, the Oxide-based Resistive Random Access Memory (OxRAM) can be used as the memory element, which is inherently tolerant against ionizing radiation and, hence, better suited for a fully hardened circuit. In this work, we propose to harden the design of an existing OxRAM-based neuron circuit through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the nMOS and pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 180-nm technology, have been carried out to validate our proposed design. In addition, we exploit two simulation setups: first, the OxRAM's behavior in a simple circuit configuration, to provide a better understanding of the OxRAM device; second, the OxRAM-based neuron circuit, to evaluate the behavior of the proposed neuron circuit hardened with ELTs. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

In this paper, we propose a sextuple cross-coupled SRAM cell, namely SCCS18T, protected against double-node upsets. Since the proposed SCCS18T cell forms a large feedback loop for value retention and error interception, the cell can provide self-recoverability from any single-node upsets (SNUs) and partial double-node upsets (DNUs). Moreover, the proposed cell has optimized operation speed due to the use of six access transistors. Simulation results show that the SCCS18T cell can save approximately 65% read access time at the cost of 49% power dissipation and 50% silicon area on average, compared with typical hardened SRAM cells.

This paper proposes a cost-effective, high-impedance-state (HIS)-insensitive, triple-node-upset (TNU)-tolerant and single-event-transient (SET)-filterable latch, namely HITTSFL, to ensure high reliability with low-cost. The latch mainly comprises an output-level SET-filterable Schmitt-trigger and three inverters that make the values stored in three parallel single-node-upset (SNU)-recoverable dual-interlocked-storage-cells (DICEs) converge at a common node to tolerate any possible TNU. The latch does not use C-elements to be insensitive to the HIS. Simulation results demonstrate the TNU-tolerability and SET-filterability of the proposed HITTSFL latch. Moreover, due to the use of clock-gating technologies and fewer transistors, the proposed latch can reduce delay, power, and area by 76.65%, 6.16%, and 28.55%, respectively, compared with the state-of-the-art TNU hardened latch (TNUHL) that cannot filter SETs.

Approximate Integrated Circuits (AxICs) have emerged in the last decade as an outcome of Approximate Computing (AxC) paradigm. AxC focuses on efficiency of computing systems by sacrificing some computation quality. As AxICs spread, consequent challenges to test them arose. On the other hand, the opportunity to increase the production yield emerged in the AxIC context. Indeed, some particular defects in the manufactured AxIC might not catastrophically impact the final circuit quality. Therefore, some defective AxICs might still be acceptable. Efforts to detect favorable conditions to consider defective AxICs as acceptable - with the goal to increase the production yield - have been done in last years. Unfortunately, the final achieved yield gain is often not as high as expected. In this work, we propose a methodology to actually achieve a yield gain as close as possible to expectations, by proposing a technique to suitably apply tests to AxICs. Experiments carried out on state-of-the-art AxICs show yield gain results very close to the expected ones (i.e., between 98% and 100% of the expectations).

Today, the concept of approximation in computing is becoming more and more a “hot topic” to investigate how computing systems can be more energy efficient, faster, and less complex. Intuitively, instead of performing exact computations and, consequently, requiring a high amount of resources, Approximate Computing aims at selectively relaxing the specifications, trading accuracy off for efficiency. While Approximate Computing gives several promises when looking at systems' performance, energy efficiency and complexity, it poses significant challenges regarding the design, the verification, the test and the in-field reliability of Approximate Computing systems. This tutorial paper covers these aspects leveraging the experience of the authors in the field to present state-of-the-art solutions to apply during the different development phases of an Approximate Computing system.

In the last decade, Approximate Computing has become a trend topic for several error tolerant applications. In this context, the use of such paradigm for reducing the area and power cost of conventional fault tolerant schemes (i.e. Triple Modular Redundancy) has been investigated recently. Unfortunately, existing solutions cannot ensure the same level of reliability compared to conventional TMR. In this paper, we propose a novel fully robust approximation-based solution suitable for safety-critical applications that can reduce the cost compared to conventional TMR structures. This solution is based on the use of four approximate modules with an overall smaller area overhead compared to a TMR made of three precise modules. The main constraint is that, for a given output of the precise module, at least three approximate modules (among four) can feed the voter with the same output. In order to build our Quadruple Approximate Modular Redundancy (QAMR) structure, we use a simple and random process whose goal is to remove different outputs with the corresponding fan-in logic from each approximate module in such a way that the above constraint is satisfied. The majority voter and its mode of operation remains the same as in the TMR. To validate our approach, we conducted experiments and results demonstrate that it is possible to achieve the fault tolerance of a full TMR approach while reducing the area overhead up to 24.28%.

In this paper, we propose a new framework for cell-aware defect diagnosis of customer returns based on supervised learning. The proposed method comprehensively deals with static and dynamic defects that may occur in real circuits. A Naive Bayes classifier is used to precisely identify defect candidates. Results obtained on benchmark circuits, and comparison with a commercial cell-aware diagnosis tool, demonstrate the efficiency of the proposed approach in terms of accuracy and resolution.

Systems on a chip have seen their surface area increased by a factor of 10 and their consumption multiplied by 5 during the last ten years. Each technological node that enabled this integration has also added new constraints challenging the overall system reliability. In addition, the integration of analog/RF blocks adds specific issues, in particular the high cost of the required test equipment. It is therefore necessary to improve test and reliability solutions in order to guarantee the production yield and the system life-time. Moreover, the massive increase in the use of communicating systems has introduced security as a cornerstone of their development. The entire hardware production flow is therefore subject to security and trust issues requiring the development of dedicated test solutions. In this paper, we focus on LIRMM contributions in the HADES project especially with details on Embedded Test Instruments (ETIs) for reliability of digital ICs, low-cost RF test based on indirect DC measurements or digital ATE capture, management of secure scan access.

Memory system reliability is a serious concern in many systems today and is becoming more worrisome as technology scales, system size grows and the demand of aggressive voltage reduction becomes more stringent. Thus, disposing of memory repair architectures with strong fault tolerance capability at low cost is desirable. In this context, Error Correcting Codes (ECC)-based repair techniques were proposed and offer aggressive reduction of the repair cost for high defect densities. However, an important issue in advanced process nodes is the fact that, single particles induce Single-Event Upsets (SEUs) in neighbor memory cells, thus leading to Multi-Cell Upsets (MCUs) and Multi-Bit Upsets (MBUs), when they occur in the same memory word. In the case of memories, there exist efficient approaches mitigating this kind of MBUs, in particular the use of interleaving. But when a memory is repaired, the impact of MBUs on the circuitry repairing the faulty memory words should also be mitigated. This can be done by using a repair Content Addressable Memory (CAM) having interleaving at its data-words, or else an Offset CAM. In this paper we present and evaluate a novel repair approach that uses the Offset CAM in ECC-based Memory Repair and hence permits the mitigation of the MBUs affecting it.

Aging and soft errors are the two most critical reliability issues for nanoscale CMOS circuits. The soft error becomes more severe if the circuit performance degraded with the aging. In this paper, we address the issue of analyzing the effects of Negative Bias Temperature Instability (NBTI) mechanisms on Integrated Circuit's (ICs') soft error susceptibility. We first analyzed the critical charge sensitivity of two-input NAND gate for various operating temperatures with three years of stress. Results show that the critical charge decreases with the temperature and has the maximum degradation of 19.98% if the input AB is at 01 logic compare to 12.06%, 16.8%, and 11.15% for 00, 10, and 11. Further, we validated the results with c17 from ISCAS'85 benchmark suite to estimate the soft error. The critical charge at the sensitive node of the c17 circuit is decreased by 9.87% for the worst case input pattern 00010. Thus thorough investigation of the critical charge provides a measure for the soft error susceptibility with the NBTI effect on ICs.

Brain-inspired computing architectures, brought by Artificial Neural Networks (ANNs), are an attractive solution to reduce the energy consumption of the conventional von Neumann's computation, with an excellent parallel processing capability. Therefore, critical applications, such as Space & Satellite, which impose severe constraints in terms of power consumption and computing efficiency, are excellent candidates to embed such networks. Nonetheless, integrated circuits operating during long-term and cumulative exposure to incidence levels of ionizing radiation may have their physical components degraded, thus drastically reducing their reliability and expected lifetime. A possible solution to enhance the radiation hardening characteristics of a conventional bulk CMOS device is to use the non-standard gate geometry referred to as Enclosed Layout Transistor (ELT). In this work, we propose to harden the design of an existing OxRAM-based neuron circuit [1] through the inclusion of ELTs, i.e., to improve the radiation hardening characteristics of a preexistent convenient neuron circuit topology by using the enclosed gate geometry for the n,pMOS devices. Electrical simulations, considering a standard commercial bulk CMOS fabrication process, in a 1SO nm technology, have been carried out to validate our proposed design. The simulation results, supported by the analysis of former works regarding the incidence of ionizing radiation in OxRAM and ELTs, indicate that the proposed hardened neuron circuit is a feasible solution to embed neuromorphic computing in aerospace applications.

This paper presents a novel dual-interlocked storage-cell (DICE)-based double-node-upset (DNU) self-recoverable, namely DURI-FF, in the nano-scale CMOS technology. The master latch of the DURI-FF cell consists of three transmission gates (TGs) and three interlocked DICEs with three common nodes. The common nodes are connected to TGs for value initialization. The slave latch of the DURI-FF cell comprises six TGs, six inverters and three interlocked DICEs. The outputs of the inverters respectively feed the internal nodes of the slave latch. The interlocked DICEs make the master latch and the slave latch DNU self-recoverable. Simulation results validate the DNU self-recoverability of the proposed DURI-FF cell. Moreover, compared with the state-of-the-art hardened flip-flop cells, the proposed DURI-FF cell achieves roughly 43% delay reduction at the cost of moderate silicon area and power dissipation.

In this paper, a highly reliable SRAM cell, namely SESRS cell, is proposed. Since the cell has a special feedback mechanism among its internal nodes and has more access transistors compared to a standard SRAM cell, the SESRS cell provides the following advantages: (1) it can self-recover from single node upsets (SNUs) and double-node upsets (DNUs); (2) it can reduce power consumption by 49.78% and silicon area by 7.92%, compared with the only existing SRAM cell which can self-recover from all possible DNUs. Simulation results validate the robustness of the proposed SESRS cell. Moreover, compared with the state-of-the-art hardened SRAM cells, the proposed SESRS cell can reduce read access time by 61.93% on average.

Diagnosis is crucial in order to establish the root cause of observed failures in Systems-on-Chip (SoC). In this paper, we present a new framework based on supervised learning for cell-aware defect diagnosis of customer returns. By using a Naive Bayes classifier to accurately identify defect candidates, the proposed flow indistinctly deals with static and dynamic defects that may occur in actual circuits. Results achieved on benchmark circuits, as well as comparison with a commercial cell-aware diagnosis tool, show the effectiveness of the proposed framework in terms of accuracy and resolution. Moreover, the proposed flow has been experimented and validated on industrial circuits (two test chips and one customer return from STMicroelectronics), thus corroborating the results achieved on benchmark circuits.

Approximate computing (AxC) is increasingly emerging as a new design paradigm to produce more efficient computation systems by judiciously reducing the computation quality. In particular, AxC has been successfully applied to integrated circuits (ICs), in the last years. Hence, concerning the test of such new class of ICs, namely approximate ICs (AxICs), new challenges-as well as new opportunities-have emerged. In this survey, we provide a thorough analysis of issues related to test procedures for AxICs and review the state-of-the-art techniques to deal with them. We resort to an illustrative example having the twofold aim of: 1) guiding the reader through the AxIC testing challenges and 2) illustrating the existing solutions to correctly overcome them, while suitably taking advantage of opportunities coming from approximation. We analyze experimentally the most recent testing techniques for AxICs and highlight their mature aspects, as well as their shortcomings. Experimental outcomes show that the testing process for AxIC is not completely mature. Indeed, only under specific conditions existing testing procedures achieve good results.

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency.

To meet the requirements of both cost-effectiveness and high reliability for safety-critical terrestrial applications, this paper proposes a novel radiation hardened latch design, namely HLCRT. The HLCRT latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has correct values on its output node, i.e., the latch is effectively DNU hardened. Simulation results demonstrate the DNU tolerance of the proposed latch. Moreover, due to the use of fewer transistors, clock gating technologies, and a high-speed path, the proposed latch saves about 444.80% delay, 150.50% power, 72.66% area, and 2029.63% delay-power-area product on average, compared with state-of-the-art DNU hardened latch designs.

The Aggressive technology scaling makes modern advanced SRAMs more and more sensitive to soft errors that include single-node upsets (SNUs) and double-node upsets (DNUs). This paper presents a novel Sextuple Cross-Coupled SRAM cell, namely SCCS cell, which can tolerate both SNUs and DNUs. The cell mainly consists of six cross-coupled input-split inverters, constructing a large error-interceptive feedback loop to robustly retain stored values. Since the cell has many redundant storage nodes, the cell achieves the following robustness: (1) the cell can self-recover from all possible SNU; (2) the cell can self-recover from partial DNUs; (3) the cell can avoid the occurrence of other DNUs due to node-separation. Simulation results validate the excellent robustness of the proposed cell. Moreover, compared with the state-of-the-art typical existing hardened cells, the proposed cell achieves an approximate 61% read access time as well as 12% write access time reduction at the costs of 47% power dissipation as well as 44% silicon area on average.

In critical (e.g. automotive) applications, Systems-on-Chip (SoC) failures that occurred during mission mode (in the field) are the most critical since they may lead to catastrophic effects. In this context, diagnosis is crucial in order to establish the root cause of observed failures with the best accuracy. With the advent of very deep submicron technologies (i.e. 7 nm), achieving such level of accuracy will become more and more difficult with today's intra-cell diagnosis tools based on effect-cause or cause-effect paradigms. This will compromise the success of subsequent Physical Failure Analysis (PFA) done on defective SoCs. Machine Learning (ML) is now used in numerous classification problems where the knowledge on some data can be used to classify a new instance of such data. In particular, several ML-based solutions exist to address volume diagnosis for yield improvement. These learning-guided diagnosis approaches start from an existing set of defect candidates and try to minimize this set (eliminate bad candidates) owing to the use of ML tools and numerous data collected during production test (e.g. thousands of failed chips with candidates correctly labeled). Although efficient in volume diagnosis, these approaches cannot be used to identify the root cause of failures in customer returns, since only one failed chip is investigated in this case, with no information about the defective behavior of some other similar chips used in the same conditions (environment, workload, etc.). In this paper, we propose a new learning-guided approach for diagnosis of mission mode failures in customer returns. The proposed approach directly produces a minimum set of good candidates derived from the application of the learning-guided intra-cell diagnosis flow. Results obtained on a set of benchmark circuits, and comparison with a commercial intra-cell diagnosis tool, show the feasibility, effectiveness and accuracy of the proposed approach.

Approximate Computing (AxC) emerges more and more as a new paradigm for the design of energy-efficient Integrated Circuits (ICs) at the cost of accuracy reduction. The latter has to be modeled and quantified by means of Error Metrics. From the testing point of view, AxC Integrated Circuits offer an opportunity. Instead of testing for all manufacturing defects, the goal is to test only for those that will lead to an error considered as not acceptable by the adopted Error Metrics. The main advantages are the test cost reduction, since the number of required test vectors will be reduced, and the yield improvement. We developed three approaches for generating test vectors targeting AxC Integrated Circuits. This paper aims at comparing these approaches on a public benchmark suite.

In today's electronic designs, more and more memories are embedded in a single chip. The latest technologies make them denser and thus defects due to the manufacturing process are more prone to occur not only in the array but also in the periphery of the memory. A fast and accurate localization of such defects has become much more difficult with traditional diagnosis approaches that do not allow a fast-enough yield learning and improvement. This paper describes a new and automated intra-cell diagnosis flow for SRAMs to precisely determine the root cause of observed failures during test. Based on the electrical and topological fault signatures obtained through traditional methods, each potential fault on the identified active nets is automatically simulated to retrieve the best defect candidates to precisely guide the Failure Analysis phase. The proposed intra-cell diagnosis flow has been experimented on simulated test cases as well as silicon (industrial) test cases. The results obtained demonstrate the effectiveness of the diagnosis flow in terms of low number of defect candidates. Moreover, for the silicon test cases, these diagnosis results match with the ongoing Failure Analysis reports.

In the recent years, Approximate Computing (AC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AC is based on the intuitive observation that, while performing exact computation requires a high amount of resources, allowing a selective approximation or an occasional relaxation of the specification can provide significant gains in energy efficiency. This work starts from the consideration that AC-based systems can intrinsically accept the presence of faulty hardware (i.e., hardware that can produce errors). In other words, an AC-based system does not need to be built using defect-free ICs. Under this assumption, we can relax test and reliability constraints of the manufactured ICs. One of the ways to achieve this goal is to test only for a subset of faults instead of targeting all possible faults. In this way, we can reduce the manufacturing cost since we reduce the number test patterns and thus the test time. We call this approach Approximate Test (AT). The main advantage is the fact that we do not need a prior knowledge of the application. Therefore, the proposed approach can be applied to any kind of IC, reducing the test time and increasing the yield. In this work, we aim at validating the proposed AT by comparing it with a functional approach. We present preliminary results on some simple case studies. The main goal is to show that by letting some faults undetected we can save test time without having a huge impact on the application quality.

Power management techniques are applied at high abstraction levels to reduce chip power consumption. Accurate and efficient power models are needed as early as possible in the design flow to ensure that correct saving decisions are taken. However, accuracy at those levels cannot be ensured, as there is not exact knowledge of the circuit structure. Then, power models based on estimation techniques at lower abstraction levels are desired. In this work, we propose a hybrid power modeling approach based on an effective library characterization methodology and an efficient power estimation flow to accurately assess gate-level power consumption. The main idea is to enhance the high-level power models by providing realistic information of the physical design. We perform experiments on ISCAS'85 benchmark circuits synthesized with a 28nm FDSOI technology. To prove the validity of our approach, we compare our results with SPECTRE simulations and show that we can achieve a 144X speedup on the runtime with a transistor-like accuracy.

Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage. The main goal of this paper is to investigate the static test compaction of a given set of functional test programs. The investigation aims at understanding and determining how to select the best functional test program candidates to obtain the smallest set having the best fault coverage. Results carried out on two different microprocessors show that a 49% reduction in test length and a 28.7% reduction in test application time can be achieved.

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art susceptibility estimation methods makes it unscalable with design complexity. In this paper we introduce a low-cost susceptibility analysis methodology that helps identifying the most vulnerable circuit elements for hardening with less computational effort and orders of magnitude faster. Our experimental results show that the methodology offers huge gain in terms of computational effort (2,500× faster) in comparison with a fault-injection based method and produces results within acceptable degree of accuracy.

Nowadays, power consumption is the one key factor that hinders System-on-Chip (SoC) performance. In order to reduce the power consumption, accurate and efficient power models have to be introduced early in the design flow, when most of the optimization potential is obtained. However, early accuracy cannot be ensured because of the lack of precise knowledge of the circuit structure. Current SoC design paradigm relies on Intellectual Property (IP) reuse, and low-level information about circuit components and structure is usually available. Thus, if we use this information and develop an estimation methodology that fits IP power modeling needs, the estimation accuracy at system level will be improved. This paper presents a Hybrid Power Estimation Technique (HPET). It is based on an effective library characterization methodology and an efficient hybrid power modeling approach to accurately and quickly assess gate-level power consumption. The aim is to give valuable and accurate physical information to design teams so they can ensure that the correct optimization techniques are implemented. Our approach can be used to compute both realistic instantaneous power and average power on a single simulation time. We performed experiments on different benchmark circuits synthesized using the 28nm FDSOI technology. To validate the proposed technique, we correlated our results with SPECTRE and PrimeTime-PX simulations. Our results showed that we can achieve up to 144× speedup on the simulation runtime with a mean error of about 6% and 13% for the instantaneous and average power components respectively.

Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power-gating is usually implemented by means of several power switches. Manufacturing defects affecting power switches can lead to increase the actual static power consumption and, in the worst case, they can completely isolate a functional block in the IC. Thus, efficient test and diagnosis solutions are needed. In this paper we propose a Design-for-Diagnosis architecture for Power Switches. The proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits as well as on industrial test case.

Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability of future electronic circuits and systems. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this paper we propose an effective hybrid fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipelined cores. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies run in parallel while the third one remains in standby until an error is detected. We have implemented this approach on a MIPS microprocessor as case study. Experiments show that our approach is comparable to TMR in terms of area with a notable power saving and offers a full protection against transient and permanent faults.

Fault-tolerant architectures have been widely used in industry to prevent circuit reliability from becoming a bottleneck for the development of robust high-performance and low-power systems. One such solution is a Hybrid Fault-Tolerant Architecture that offers benefits such as low power and lifetime reliability improvement. However, it has been identified that there is room of improvement in efficiency. Thus, in this paper we present design space exploration and optimization of the Hybrid Fault-Tolerant Architecture. The study involves application of four design variants to some ITC benchmark circuits as case study. Experimental results compare the initial and optimized designs and show that the proposed optimizations offer around 65% reduction in terms of area, about 55% power saving and 87% less performance overhead as compared to the initial design without any penalty of the fault tolerance capability.

In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D MPSoCs, which can increase critical path delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid hot spots. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well.

In this paper, we investigate the generation of diagnostic test vectors targeting the intra-cell defects. Experimental results carried out on an industrial circuit show that we actually increase the diagnosis resolution by adding few more diagnostic test patterns.

Physical Design (PD) issues are becoming a major challenge with technology scaling in integrated circuits. Multi-aggressor crosstalk, power supply noise and ground bounce are some of the PD issues that cause considerable path delay variations. Therefore, these PD issues need to be considered during path delay testing to ensure better delay defect coverage. In this paper, we first show that the path delay Automatic Test Pattern Generation (ATPG) test methods are incapable of generating an input pattern that can capture worst-case path delay in circuits. We, then present our Physical Design Aware Pattern Generation (PDAPG) method to generate an input test pattern that can capture worst-case path delay in the presence of PD issues. We propose a backtrace X-filling approach to identify the relevant X-bits causing worst-case path delay. Simulations performed on ITC'99 benchmark circuits show that our PDAPG method is capable of providing high quality input test patterns in comparison with conventional path delay ATPG test methods.

With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.

Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools.

Power-gating techniques have been adopted so far to reduce the static power consumption of an Integrated Circuit (IC). Power gating is usually implemented by means of several power switches. Manufacturing defects affecting power switches can lead to increase the actual static power consumption and, in the worst case they can completely isolate a functional block of the IC. In this paper we present a novel Design for Test & Diagnosis to increase the test quality and diagnosis accuracy of power switches. The proposed approach has been validated through SPICE simulations on ITC'99 benchmark circuits.

CMOS technology trends at one side open up some opportunities like making small and power efficient devices available, which in turn allow to put more functionality into a single chip. However, on the other side it poses some challenges like making devices vulnerable to hard and soft errors. In this paper we propose an efficient fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipeline structures. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies are running in parallel while the third one remains in standby until an error is detected. We implement this approach on a MIPS microprocessor as case study to make it resilient against transient and permanent faults.

In this paper we propose a novel Power Supply Noise (PSN) sensor. It is based on timing uncertainty measure. Compared to state of the art it allows to measure the PSN events in more accurate way. The proposed sensor is actually under validation and patent reviewing process.

3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods to investigate timing variation introduced by resistive open TSVs in a critical path delay with multiple TSVs. Method I computes the correlation of multiple TSVs in a path to overall path delay to determine if TSVs are the source of the introduced delay. Method II pinpoints which TSV is faulty by computing the delay fault coverage of each TSV in a path with multiple TSVs. Our results indicate the accuracy of our proposed method and promotes early identification of resistive open defects TSVs.

Magnetic random access memory (MRAM) is an emerging technology with potential to become the universal on-chip memory. Among existing MRAM technologies, thermally assisted switching (TAS)-MRAM technology offers several advantages compared with other technologies: selectivity, single magnetic field, and high-integration density. In this paper, we analyze the impact of resistive-open defects on TAS-MRAM behavior. Electrical simulations were performed on a hypothetical 16 word TAS-MRAM architecture enabling any combination of read and write operations. Results show that read and write sequences may be affected by resistive-open defects that may induce single and double-cell faulty behaviors. As a next step, we will exploit the analyses results to guide the test phase by providing effective test algorithms targeting faults related to actual defects affecting TAS-MRAM architectures.

Design of power delivery network (PDN) is a constrained optimization problem. An ideal PDN must limit voltage drop that results from switching circuits' transients, satisfy current density constraints that arise from electromigration limits, yet use only minimal metal resources so that design density targets can be met. It should also provide an efficient thermal conduit to address heat flux. Furthermore, an ideal PDN should be a regular structure to facilitate design productivity and manufacturability, yet be resilient to address varying power demands across its distribution area. In 3-D ICs, these problems are further constrained by the need to minimize through-silicon via (TSV) area and bridge power lines of different dimensions across tiers, while addressing varying power demands in lateral and vertical directions. In this paper, we propose an unconventional power grid optimization solution that allows us to resize each tier individually by applying tier-specific constraints and yet be optimal in a multitier network, where each tier is locally resized while globally constrained. Tier-specific constraints are derived from electrical and thermal targets of 3-D PDNs. Two resizing algorithms are presented that optimize 3-D PDNs standalone or 3-D PDNs together with TSVs. We demonstrate these solutions on a three-tier setup where significant area savings can be achieved.

The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses for good chips. Different from conventional low-power BIST, this paper is the first that has explicitly focused on achieving capture power safety with a practical scheme called capture-power-safe BIST (CPS-BIST). The basic idea is to identify all possibly erroneous test responses and use the well-known technique of mask (partial-mask or full-mask) to block them from reaching the MISR. Experiments with large benchmark and industrial circuits show that CPS-BIST can achieve capture power safety with negligible impact on both test quality and area overhead.

SRAM testing is becoming more and more challenging due to issues caused by continuous device scaling. Fabricated SRAMs are submitted to random and systematic process variability, which strongly affect the cell's behavior and also the ability of test algorithms to detect faults. Traditionally, bias conditions have been used to improve the behavior of the SRAM under process variations by applying body bias to compensate for the effect of variability. Based on the same principle, bias conditions also affect the cell's behavior when resistive-opens are present, hence affecting test's defect coverage capability. Both body- and source-bias conditions are analyzed in this paper to find the way to improve defect detect ability in the SRAM cell. Source-biasing has been proven to be the more effective of the two, leading to more than 3X improvement of the defect detected value. Also, by adapting the source-bias conditions to process parameter values, over- and under-testing of the SRAM can be avoided.

Low-power SRAMs embed mechanisms for reducing static power consumption. When the SRAM is not accessed during a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cells as low as possible without data loss. Thus, faulty-free behavior of the voltage regulator is crucial for ensuring data retention in core-cells when the SRAM is in low-power mode. This paper investigates the root cause of data retention faults due to voltage regulator malfunctions. This analysis is done under realistic conditions (i.e., industrial core-cells affected by process variations). Based on this analysis, we propose an efficient test flow for detecting data retention faults in low-power SRAMs.

Three-dimensional stacking technology promises to solve the interconnect bottleneck problem by using Through-Silicon-Vias (TSVs) to vertically connect circuit layers. However, manufacturing steps may lead to partly broken or incompletely filled TSVs that may degrade the performance and reduce the useful lifetime of a 3D IC. Due to combinations of physical factors such as switching activity, supply noise and crosstalk, path delays can experience speed-up or slow-down that could let the effect of resistive open TSV go undetected by conventional test methods. In this work, we present a metric based on probabilistic analysis to detect delay defects induced by resistive opens that occur on signal line TSVs. Our experimental result will show the accuracy of the proposed metric.

Functional operations of a Static Random Access Memory (SRAM) are strongly affected by random variability in core-cell transistors and by the variability-induced threshold voltage mismatch between the transistors of the Input-Output (IO) circuitry (especially Sense Amplifiers). This variability also affects the faulty behavior of the SRAM array. This paper is focused on the analysis of static and dynamic faults due to resistive-open defects in the SRAM core-cell, taking into account the effects of random process variability in core-cells and IO circuitry. Statistical analyses have been performed to evaluate the SRAM failure probabilities accounting for defects at each possible location. The results show that random process variability in the SRAM core-cell and IO circuitry have an important effect on the behavior of an SRAM array and also on the defect coverage of various commonly-used test sequences. It is shown that under variability, the minimum defect size detected with maximum probability is more than 2X larger than the minimum size detected in nominal conditions, thus leaving a large range of defects undetected. Several stress conditions during test have been evaluated to assess their capability to increase the defect coverage under random process variability.

In current technologies, the robustness of Static Random Access Memories (SRAM) has to be investigated under any possible source of disturbance. In this paper, we evaluate the reliability of an SRAM cell exposed to atmospheric neutron radiation, affected by random threshold voltage variation and under different operation conditions (supply voltage, process corner and temperature). The SRAM cell's Soft Error Rate (SER) at simulation level is estimated using accurate models of atmospheric neutron induced currents. The study shows that in extreme operation conditions and under random process variability, the SER of an SRAM can reach values up to 3X larger than the nominal value, or down to 2X smaller than the nominal value. This large SER range confirms the importance of our study and justifies the need for further evaluation of circuits under radiation at the simulation level.

Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper analyzes two assist techniques: word line level reduction and negative bit line boost. The analyzed assist techniques improve read stability and write margin of core-cells when the SRAM operates at a lowered supply voltage. In this work, we investigate the impact of such assist techniques on the faulty behavior of low-power SRAMs. This analysis is based on extensive injection of resistive-open and resistive-bridging defects in core-cells of a commercial low-power SRAM. Our study determines the most stressful configuration of assist circuits to detect each faulty behavior induced by injected defects. We show that, by applying most stressful configurations of assist circuits during test phase, defect coverage can be increased up to 89% w.r.t. test solutions that do not exploit assist circuits. Based on this analysis, we present an efficient test solution that exploits the configuration of assist circuits as a parameter to maximize the detection of studied defects, while reducing time complexity up to 73% w.r.t. test flows using state-of-the-art test algorithms.

Voltage regulation systems offer an efficient mechanism for reducing static power consumption of SRAMs. When the SRAM is not accessed for a long period, it switches into an intermediate low-power mode. In this mode, a voltage regulator is used to reduce the voltage supplied to the core-cell array as low as possible without data loss. Therefore, reliable operation of such device must be ensured by using adequate test techniques. In this work, we propose low area overhead built-in self-test (BIST) and built-in self-repair (BISR) schemes that can be embedded on the SRAM to automatically test and repair the voltage regulator. Simulation results prove the effectiveness of the proposed technique for detecting, diagnosing and repairing voltage regulators of low-power SRAMs.

Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obscure the rapport between supply noise and path delay and make the selection of stimuli for worst case path delay a difficult task during test pattern generation. In this paper, we utilize power supply noise and ground bounce distribution along with physical design data to generate test patterns for capturing worst case path delay. We propose accurate close-form mathematical models for capturing the effect of power supply noise and ground bounce on path delay. These models are based on modified nodal analysis formulation of power and ground networks, where current waveforms are obtained from levelized simulation and cell library characterization. The proposed test pattern generation flow is a simulated-annealing-based iterative process, which utilizes mathematical models for capturing the impact of supply noise on path delay for a given input pattern. We perform experiments on ITC'99 benchmarks and show that path delay variation can be considerable if test patterns are not properly selected.

3-D integration presents a path to higher performance, greater density, increased functionality and heterogeneous technology implementation. However, 3-D integration introduces many challenges for power and thermal integrity due to large switching currents, longer power delivery paths, and increased parasitics compared to 2-D integration. In this work, we provide an in-depth study of power and thermal issues while incorporating the physical design characteristics unique to 3-D integration. We provide a qualitative perspective of the power and thermal dissipation issues in 3-D and study the impact of Through Silicon Vias (TSVs) size for their mitigation. We investigate and discuss the design implications of power and thermal issues in the presence of decoupling capacitors, TSV/on-die/package parasitics, various resonance effects and power gating. Our study is based on a ten-tier system utilizing existing 3-D technology specifications. Based on detailed power distribution and heat dissipation models, we present a comprehensive analysis of TSV tapering for alleviating power and thermal integrity issues in 3-D ICs.

Magnetic Random Access Memory (MRAM) is an emerging memory technology. Among existing MRAM technologies, the Thermally Assisted Switching (TAS) MRAM technology offers several advantages such as selectivity, single magnetic field and high integration density. In this paper, we analyze resistive-bridge defects that may affect the TAS-MRAM architecture. Electrical simulations were performed on a hypothetical 16-words TAS-MRAM architecture enabling any sequences of read/write operations. Results show that both read and write operations may be affected by these defects. Especially, we demonstrate that resistive-bridge defects may have a local (single cell) or global (multiple cells) impact on the TAS-MRAM functioning. As these analysis results will be further used to develop effective test algorithms targeting faults related to actual resistive bridge-defects that may affect TAS-MRAM architecture.

High peak power consumption during test may lead to yield loss. On the other hand, reducing too much test power may lead to test escape. In order to overcome this problem, test power has to mimic the power consumed during functional mode, being as high as possible but not crossing the frontier of over-consumption. Measuring power consumption is a very time consuming activity, therefore many works in the literature focused on the indirect ways to provide power consumption estimation in a fast manner. In this paper we concentrate on a similar issue, concentrating our effort on devising a fast method for the identification and estimation of the peak power produced by test patterns. In particular we provide a detailed discussion on case studies related to peak power estimation of CPU cores when executing functional patterns, the proposed method uses the gate-level description of the CPU to identify a subset of time points over the entire test pattern that are showing the most significant peak power values. The proposed methodology has been validated on two case studies synthesized in a 65nm industrial technology.

Managing the power consumption of circuits and systems is challenging not only during functional operations but also during manufacturing test. In this paper, we first explain why it is important to control power consumption during test application. We will introduce the basic concepts and discuss issues arising from excessive power dissipation during test. Then, we explain how it is possible to control power consumption during test. We will provide an overview of existing structural and algorithmic solutions for power-aware testing, and we will show how low power circuits can be tested safely without affecting yield and reliability.

In this work, we present a new power supply noise sensor based on timing uncertainty measurements. The proposed sensor can detect power supply noise events in a more accurate way compared to the state of the art solutions. Experimental results validated the efficiency of the proposed approach.

Magnetic Random Access Memory (MRAM) is an emerging technology with the potential to become the universal on-chip memory. Among the existing MRAM technologies, the Thermally Assisted Switching (TAS) MRAM technology offers several advantages compared to the others technologies: selectivity, single magnetic field and integration density. As any other types of memory, TAS-MRAMs are prone to defects, so TAS-MRAM testing needs definitely to be investigated since only few papers can be found in the literature. In this paper we analyze the impact resistive-open defects on the heat current of a TAS-MRAM architecture. Electrical simulations were performed on a hypothetical 4×4 TAS-MRAM architecture enabling any read/write operations. Results show that W0 and/or W1 operations may be affected by the resistive-open defects. This study provides insights into the various types of TAS-MRAM defects and their behavior. As future work, we plan to utilize these analyses results to guide the test phase by providing effective test algorithm targeting fault related to actual defects that may affect TAS-MRAM architecture.

Thermally Assisted Switching Magnetic Random Access Memory (TAS-MRAM) is an emerging technology that offers several advantages compared to existing non-volatile memory technologies. In this paper we show how coupling faults induced by resistive-open defects impact the TAS-MRAM architecture. Results shows that read and write operations may be affected these defects and may induce single and double cell faulty behaviors.

Three-dimensional (3D) integration is a fast emerging technology that offers integration of high density, fast performance and heterogeneous circuits in a small footprint. Through-Silicon-Vias (TSVs) enable 3D integration by providing fast performance and short interconnects among tiers. However, they are also susceptible to defects that occur during manufacturing steps and cause crucial reliability issues. In this paper, we perform an analysis of resistive-open defects (ROD) on TSVs considering coupling effects (i.e. inductive and capacitive) and a wide frequency spectrum. Our experiments show that both substrate coupling and switching frequency can have a significant impact on weak open TSV behavior.

Summary form only given. Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is applied in SRAMs using power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This paper provides a detailed analysis based on electrical simulations to describe the impacts of resistive-open defects on the power mode control logic, which generates control signals of power switches.

Electronic system reliability over soft errors is very critical as the transistor size shrinks. Many recent works have defined the device error rate under radiation for SRAMs in hold mode (static) and during operation (dynamic). This paper evaluates the impact of running test algorithms on SRAMs exposed to neutron radiation in order to define their stressing factor. The results that we show are based on experiments performed at the TSL facility in Uppsala, Sweden using a Quasi-Monoenergetic neutron beam. The evaluation of the test algorithms is based on the calculated device SEU cross section.

This paper proposes a novel scheme to manage capture power in a pinpoint manner for achieving guaranteed capture power safety, improved small-delay test capability, and minimal test cost impact in at-speed scan test generation. First, switching activity around each long path sensitized by a test vector is checked to characterize it as hot (with excessively-high switching activity), warm (with normal/functional switching activity), or cold (with excessively-low switching activity). Then, X-restoration/X-filling-based rescue is conducted on the test vector to reduce switching activity around hot paths. If the rescue is insufficient to turn a hot path into a warm path, mask is then conducted on expected test response data to instruct the tester to ignore the potentially-false test response value from the hot path, thus achieving guaranteed capture power safety. Finally, X-restoration/X-filling-based warm-up is conducted on the test vector to increase switching activity around cold paths for improving their small-delay test capability. This novel approach of pinpoint capture power management has significant advantages over the conventionalapproachofglobalcapturepower management, as demonstrated by evaluation results on large ITC'99 benchmark circuits and detailed path delay analysis.

Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is implemented through power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This way, one or more memory blocks can be disconnected from the power supply during a long period of inactivity, thus reducing static power consumption. This paper focuses on low-power SRAMs, and in particular, the power gating mechanisms of core-cells and peripheral circuitry. We provide a detailed analysis based on electrical simulations to characterize the impact of resistive-open defects on the power mode control logic. Based on this analysis, we introduce appropriate fault models that represent the observed faulty behaviors. Finally, we propose an efficient test solution targeting the set of identified fault models.

Memory design and test represent very important issues. Memories are designed to exploit the technology limits to reach the highest storage density and high-speed access. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects. The challenge of testing SRAM memories consists in providing realistic fault models and test solutions with minimal application time. Due to the complexity of the memory device, fault modeling is not trivial. Classical memory test solutions cover the so-called `static faults' (such as stuck-at, transition, and coupling faults) but are not sufficient to cover faults that have emerged in latest VDSM technologies and which are referred to as `dynamic faults'. This tutorial aims at introduce and guide to new test approaches developed so far for dealing with dynamic faults in the latest generation of SRAM memories.

Although CMOS technology scaling offers many advantages, it suffers from robustness problem caused by hard, soft and timing errors. The robustness of future CMOS technology nodes must be improved and the use of fault tolerant architectures is probably the most viable solution. In this context, Duplication/Comparison scheme is widely used for error detection. Traditionally, this scheme uses a static comparator structure that detects hard error. However, it is not effective for soft and timing errors detection due to the possible masking of glitches by the comparator itself. To solve this problem, we propose a pseudo-dynamic comparator architecture that combines a dynamic CMOS transition detector and a static comparator. Experimental results show that the proposed comparator detects not only hard errors but also small glitches related to soft and timing errors. Moreover, its dynamic characteristics allow reducing the power consumption while keeping an equivalent silicon area compared to a static comparator. This study is the first step towards a full fault tolerant approach targeting robustness improvement of CMOS logic circuits.

Launch-off-Capture (LOC) and Launch-off-Shift (LOS) are the two main test schemes for at-speed scan delay testing. In the literature, it has been shown that LOS has higher performance than LOC in terms of fault coverage and test length, but higher peak power consumption during the launch-to-capture cycle. Power reduction seems to be the key to really exploit LOS test scheme. However, it has been proven that reducing too much test power can lead to test escape due to under-test. In this context, this study proposes a smart X-filling framework able to adapt peak power consumption during the launch-to-capture cycle according to the functional power, i.e. the power consumption of the circuit in functional mode. Here, the main goal is to obtain a final test set with peak power consumption as close as possible to the functional power. Experimental results, carried out on the well-known ITC'99 benchmarks, prove the feasibility of the proposed approach.

It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been proposed, and several of X-filling techniques have proven especially effective. With X-filling in the launch-off shift (LOS) scheme, however, adjacent-fill (which was originally proposed for shift-in power reduction) is used frequently. In this work, we propose a novel X-filling technique for the LOS scheme, called Adjacent-Probability-based X-Filling (AP-fill), which can reduce more LTC power than adjacent-fill. We incorporate AP-fill into a post-ATPG test modification flow consisting of test relaxation and X-filling in order to avoid the fault coverage loss and the test vector count inflation. Experimental results for larger ITC'99 circuits show that the proposed AP-fill technique can achieve a higher power reduction ratio than 0-fill, 1-fill, and adjacent-fill.

In this paper, a novel hybrid fault tolerant architecture for digital circuits is proposed in order to enable the use of future CMOS technology nodes. This architecture targets robustness, power consumption and yield at the same time, at area costs comparable to standard fault tolerance schemes. The architecture increases circuit robustness by tolerating both transient and permanent online faults. It consumes less power than the classical Triple Modular Redundancy (TMR) approach while utilizing comparable silicon area. It overcomes many permanent faults occurring throughout manufacturing while still tolerating soft errors introduced by particle strikes. These can be done by using scalable redundancy resources, while keeping the hardened combinational logic circuits intact. The technique combines different types of redundancy: information redundancy for error detection, temporal redundancy for soft error correction and hardware redundancy for hard error tolerance. Results on largest ISCAS and ITC benchmark circuits show that our approach has an area cost negligible of about 2% to 3% with a power consumption saving of about 30% compared to TMR. Finally, it deals with aging phenomenon and thus, increases the expected lifetime of logic circuits.

Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.

The Flash technology is the most popular non-volatile memory technology. In this paper, we present the ability of a SPICE-like model of the ATMEL TSTAC™ eFlash technology to guide the design and test phases. This model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. It is able to guide the test phase since it allows analyzing and modeling defects that may affect the eFlash array. This analysis highlights the interest of the proposed model to identify a realistic set of fault models that has to be tested, thus enhancing existing solutions for TSTAC™ eFlash testing. The proposed model is also helpful to guide the design phase. Data presented in the paper demonstrate its accuracy compared to silicon measurements, usefulness to predict the technology shrinking and usefulness to guide the pulse programming method.

As technology scales down, the effects of power supply noise and ground bounce are becoming significantly important. In the existing literature, it has been shown that excessive power supply noise can affect the path delay, while ground bounce is either neglected or assumed similar to power supply noise. In this work, we present a detailed study of combined and uncorrelated power supply noise and ground bounce and their impact on the path delay. Our analyses show that different combination of power supply noise and ground bounce can lead to either delay speed-up or slow-down. Furthermore, our study shows the degrading influence of supply noise resonance on the path delay. We perform HSPICE simulations for path delay analysis on various technology nodes i.e. 130nm, 90nm, 65nm and 45nm.

A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-of-the-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.

High power consumption during test may lead to yield loss and premature aging. In particular, excessive peak power during at-speed delay fault testing represents an important issue. In the literature, several techniques have been proposed to reduce peak power consumption during at-speed LOC or LOS delay testing. On the other hand, some experiments have proved that too much test power reduction might lead to test escape and reliability problems. So, in order to avoid any yield loss and test escape due to power issues during test, test power has to map the power consumed during functional mode. In literature, some techniques have been proposed to apply test vectors that mimic functional operation from the switching activity point of view. The process consists of shifting-in a test vector (at low speed) and then applying several successive at-speed clock cycles before capturing the test response. In this paper, we propose a novel flow to determine the functional power to be used as test power (upper and lower) limits during at-speed delay testing. This flow is also used for comparison purpose between the above-mentioned test scheme and power consumption during the functional operation mode of a given circuit. The proposed methodology has been validated on an Intel MC8051 micro controller synthesized in a 65 nm industrial technology.

This paper proposes an innovative approach to cope with defects in SRAM bit-cell array. Traditional approaches use spare parts (rows, columns or blocks) to replace defective bit-cells. Instead of replacing defective bit-cells, we propose to operate the SRAM with reduced storage capacity whenever defective bit-cells are present. We implement this feature through a programmable combinational logic, called Scrambling Module (SM), which scrambles the memory addresses. The scrambling changes the addresses of the defective bit-cells, grouping them in an idle address zone located at the end of the memory address plan. The SM is described by using a mathematical formulation based on linear algebra. The proposed technique can be used in combination with traditional redundancy approaches using spare rows and/or columns. The effectiveness of three different SM is demonstrated, considering a 1MBit SRAM. For a given level of defect tolerance, it is shown that our technique can reduce the amount of spare area by several orders of magnitude. Moreover, as the SM is implemented as an external block, it does not affect the maximum operation frequency of the SRAM. Instead, it affects the memory access delay.

At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.

This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

This paper introduces a simulator that allows analyzing the radiation induced errors on memory devices. The simulator takes all the radiation effects on SRAM into account and can be easily tuned on the base of data gained during radiation experiments and/or presented in literature. We also present a case study application in which the proposed simulator is used to validate a low-cost hardware platform for soft error detection in avionic environment by the mean of atmospheric balloons in the context of HAMLET project.

Reliability analysis of SRAM core-cells requires statistical methods with very high accuracy to cope with very low failure probabilities. Although new statistical methods have been recently proposed, to the best of our knowledge, there is no method able to evaluate the joint failure probability (the probability that at least one failure mechanism occurs) of an SRAM core-cell with enough accuracy in a reasonable time. We propose a statistical simulation method based on the analytical integration of the multivariate Gaussian distribution function.

At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this paper, we propose a comparison between the two testing schemes in terms of transition fault coverage and power consumption, in order to quantify the pros and cons of LOS with respect to LOC. This study shows that LOS not only exhibits higher performance in coverage but also does not require as much extra power as predicted, especially in terms of peak power. These facts may represent convincing arguments for its wider use and development.

In this paper, we present a comparative study on the effects of resistive-bridging defects in the SRAM core-cells, considering different technology nodes. In particular, we analyze industrial designs of SRAM core-cell at the following technology nodes: 90nm, 65nm and 40nm. We have performed an extensive number of simulations, varying the resistive value of defects, the power supply voltage, the memory size and the temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array.

In the context of SRAM testing, we propose a methodology to define proper conditions under which SRAMs should be tested to improve their reliability. This methodology is especially suitable to deal with the impact of threshold voltage variability affecting SRAM core-cell transistors. By establishing an objective manner of comparing different test conditions, the proposed study shows how it is possible to detect SRAM core-cells with poor quality by applying a reduced set of test runs. The proposed methodology also allows determining the most appropriate DfT (Design-for-Test) technique for each peculiar SRAM design and technology.

Flash memories are based on the floating gate technology allowing the write and erase data electronically. Such a technology can be prone to complex defects leading to faulty behaviors. In this paper, we introduce an electrical model of the ATMEL TSTACTM eFlash memory technology. The model is composed of two layers: a functional layer representing the floating gate and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim tunneling effect. The proposed model has been validated by means of simulations and comparisons with ATMEL silicon data. We apply this model for the analysis of defect-induced failures. As a case study, a resistive defect injection is considered.

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In this paper, we propose a memory based test bench able to record soft errors that may occur to modern circuits in a certain environment. This system allows a good flexibility from different points of view. It is conceived to be modular, programmable, low power consuming and portable. Consequently, it can operate in various experimental conditions such as under artificial sources of particles as well as in natural ambience, from the earth surface to spatial environment.

In this paper we investigate the possibility of using commercial synthesis tools to build parity predictors for nano-electronic gates designs. They will be used as redundant resources for robustness improvement for future CMOS technology nodes.

This study investigates the reasons why test power reduction through X-filling techniques works well for cycle-average power reduction but is not so efficient concerning instantaneous peak power reduction.

Negative Bias Temperature Instability (NBTI) is a degradation phenomenon that occurs in PMOS transistors during circuit lifetime. Recent works have proposed transistor level and circuit level models that allow designers to deal with such phenomenon. Based on these models and taking into account Random Dopant Fluctuation (RDF), we study the possibility of detecting SRAM core-cells that are prone to NBTI failures during post-production test. For this purpose, we introduce a statistical simulation method that allows estimating the amount of NBTI affected core-cells that pass or fail under given test conditions. Supply voltage, temperature, word line pulse width, word line pulse voltage and bit line voltage are the parameters considered as test conditions. An industrial core-cell design with a 65 nm technology is used as case study.

This paper presents a comprehensive framework for logic diagnosis consisting of two main phases. In the first phase, a set of suspected faulty sites is obtained by applying an approach based on an Effect-Cause analysis. Then, in the second phase, a set of realistic fault models is associated with each suspected faulty site by analyzing specific information, called fault evidences, collected during the first phase. The main advantage of the proposed methodology is its capability to deal with several fault models at the same time. Another advantage is that it is able to handle both single and multiple fault occurrences. Experiments on ISCAS85, ISCAS89, and ITC99 benchmark circuits show the efficiency of the proposed method both in terms of diagnosis resolution and accuracy of the predicted fault models.

The importance of delay faults proportionally increases when entering in the nano-technology era, and logic diagnosis must localize delay faults as precisely as possible to speed-up yield ramp-up. This paper presents a logic diagnosis approach targeting delay faults. The proposed approach is based on the single-location-at-a-time (SLAT) paradigm used to determine a set of suspects. It addresses the case of sequential circuits tested at-speed. The main advantages of this approach are that it can manage a comprehensive set of delay faults, and that it is independent on the size of the delay (induced by the fault). Experimental results show the effectiveness of the proposed approach in terms of absolute number of suspects.

Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern in VDSM technologies. It provides information about the SRAM design reliability, and its effectiveness is therefore mandatory for safety applications. Existing core-cell stability design-for-test (DfT) techniques consist in controlling the voltage levels of bit lines to apply a weak write stress on the core-cell under test. If the core-cell is weak, the weak write stress induces the faulty swap of the core-cell. However, these solutions are costly in terms of area and test application time, and generally require modifications of critical parts of the SRAM (core-cell array and/or the structure generating the internal auto-timing). In this paper, we present a new DfT technique for stability fault detection. It consists in modulating the word line activation in order to perform an adjustable weak write stress on the targeted core-cell for stability fault detection. Compared to existing DfT solutions, the proposed technique offers many advantages: programmability, low area overhead, low test application time. Moreover, it does not require any modification of critical parts of the SRAM.

This paper presents a logic diagnosis approach targeting bridging faults. The proposed approach is performed in two phases, (i) a fault localization phase based on the single-location-at-a-time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. The main advantages of this approach are that the fault localization phase is fault model independent, and that the fault model allocation phase is able to deal at the same time with several bridging fault models leading to either static or dynamic faulty behaviors. Experimental results on full scan circuits show the diagnosis accuracy of the proposed approach in terms of absolute number of suspects. Moreover, a comparison with an industrial reference tool highlights the reliability of our approach.

This paper proposes an efficient technique for transition delay fault coverage measurement in synchronous sequential circuits. The proposed strategy is based on a combination of multi-valued algebra simulation, critical path tracing and deductive fault simulation. The main advantages of the proposed approach are that it is highly computationally efficient with respect to state-of-the-art fault simulation techniques, and that it encompasses different delay sizes in one simulation pass without resorting to an improved transition fault model. Preliminary results on ITC99 benchmarks show that the gain in terms of CPU time is up to one order of magnitude compared to previous existing techniques.

Embedded flash memories are dominated by the NOR architecture but NAND is becoming more and more adopted due to its high storage capacity. This paper presents a preliminary study on actual defects in NAND array.

In this paper, we present an exhaustive analysis of resistive- open defects in sense amplifiers of static random access memory designed with a 65 nm technology. We show that some resistive-open defects may lead to a new type of dynamic behavior that has never been experienced in the past. It is modeled by dynamic two-cell incorrect read faults of two different types. Such fault models represent failures in the sense amplifier, which prevent it from performing any read operations (in case of type 1 [1]) or only a single type of read operation (in case of type 2). Results of electrical simulations are presented to provide a complete understanding of such a faulty behavior and possible March test solutions are proposed to detect all d2cIRFs.

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of donpsilat care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.

Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information of fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core- cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost design-for-diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512 times 512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of write drivers (logic and analog levels on bit lines).

With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.

The usual techniques for memory diagnosis are mainly based on signature analysis. They consist in creating a fault dictionary that is used to determine the correspondence between the signature and the fault models affecting the memory. The effectiveness of such diagnosis methods is therefore strictly related to the fault dictionary accuracy. To the best of our knowledge, most of existing signature-based diagnosis approaches targets static faults only. In this paper, we present a new diagnosis approach that represents an alternative to signature-based approaches. This new diagnosis technique, named history-based diagnosis, makes use of the effect-cause paradigm already developed for logic design diagnosis. It consists in creating a database containing the history of operations (read and write) performed on a faulty memory core-cell. This information is crucial to track the root cause of the observed faulty behavior and it can be used to generate the set of possible fault primitives representing the set of suspected fault models. This new diagnosis method is able to identify static as well as dynamic faults. Although applied to SRAMs in this paper, it can be effective also for other memory types such as DRAMs. Experimental results are provided to prove the efficiency of the proposed methodology in generating a list of suspected faults as well as the location of the faulty components in the memory.

Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.

Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information on fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core- cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows to saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost design-for- diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512 times 512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of the write drivers (logic and analog levels on bit lines).

Nanoscaled SRAMs are now becoming more and more prone to device parameter deviations. In this paper, we consider threshold voltage (Vt) deviations in 6T core-cells designed with 90 nm technology. Static faults (transition and read destructive) but also dynamic faults (dynamic read destructive) are obtained as resulting faulty behaviors. Moreover, electrical data show that PVT (process, voltage, temperature) corners that maximize the detection of these faults are quite unconventional. Especially, we show that Vt deviations have their main impact at low voltage while hard defects, such as resistive-open defects in the core-cell, better manifest themselves at high voltage. This study of parameter deviations opens an additional problematic for the test of nanoscaled SRAMS that will be much more severe in deeper technologies (65 nm and 45 nm).

In this paper, we present a diagnosis methodology targeting the whole set of bridging faults leading to either static or dynamic faulty behavior. The adopted diagnosis algorithm resorts only to logic information provided by the tester without requiring a detailed description of the fault models. It is based on an Effect-Cause analysis providing a ranked list of suspects always including the root cause of the observed error. Experimental results on benchmarks ISCAS'89 and ITC '99 show the efficiency of the proposed solution in terms of diagnosis resolution and required computational time.

This paper presents an analysis of the electrical origins of slow write driver faults (SWDFs) (van de Goor et al., 2004) that may affect SRAM write drivers in 65nm technology. This type of fault is the consequence of resistive-open defects in the control part of the write driver. It involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. In the first part of the paper, we present the SWDF electrical phenomena and their consequences on the SRAM functioning. Next, we show how SWDFs can be sensitized and observed and how a standard March test is able to detect this type of fault

The embedded flash technology can be subject to complex defects creating functional faults. In this paper, we describe the different steps in the electrical modeling of 2T-FLOTOX core-cells for a good understanding of failure mechanisms. First, we present a first order electrical model of 2T-FLOTOX core-cells which is characterized and compared with silicon data measurements based on the ATMEL 0.15 mum eFlash technology. Next, we propose a study of resistive defect injections in eFlash memories to show the relevance of the proposed simulation model. At the end of the paper, a table summarizes the functional fault models for different resistive defect configurations and experimental set-ups. According to these first results and with additional analysis of actual defects presented in [1] we are then able to enhance existing test solutions for eFlash testing.

In this paper, we present an analysis of resistive-open defects in the sense amplifier of SRAMs designed with the Infineon 65 nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been published in the past. This faulty behavior can be modeled as a dynamic two-cell Incorrect Read Fault (d2cIRF). Such d2cIRF is the consequence of a failure in the sense amplifier which prevents it to perform any read operations. We show that it requires a specific sequence of read operations to be detected. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior. Finally, a possible March test solution is presented to allow the detection of d2cIRFs in all sense amplifiers of an SRAM.

This paper presents DERRIC (Diagnosis of logic ERRors in VLSI Integrated Circuits), a diagnostic tool targeting most of the fault models used in practice today. This tool is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The underlying method of DERRIC is based on the Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) that consists in identifying critical lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each critical line, so that root causes of failures can be finally determined. The main advantage of this method is that it does not need to explicitly consider each fault model during the diagnosis process. Experiments on ISCAS'85 and ITC'99 benchmarks show the efficiency of the proposed tool in terms of diagnosis resolution.

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.

High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.

The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like flash. Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. In this paper, the authors analyze the impact of a defective tunnel window oxide thickness. The authors show that this defective oxide thickness impacts erase or/and write operations as well as the retention and reliability of the eFlash. The proposed solution to detect such a defective oxide consists in using the voltage disturbance due to the coupling phenomenon existing between bit lines. This particular defective mechanism can be modeled as a coupling fault, especially a state coupling fault. Based on this analysis, the authors propose a test solution that uses two checkerboard patterns; checkerboard pattern (CKB) and its complement (CKBI). The authors show that these two patterns have to be applied by using a parallel programming approach, which allows to increase the coupling phenomenon and thus the voltage disturbance

In this paper, we present an analysis of resistive-open defects in the write driver of SRAMs designed with the Infineon 65nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been experienced in the past. This faulty behavior can be modeled as an un-restored destructive write fault (URDWF). Such URDWF is a consequence of the structural dependencies that exist between the write driver and the sense amplifier, and appears when a specific read operation is performed immediately after a specific write operation. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior and to highlight the difference with a standard un-restored write fault (URWF) model. Next, a possible March test solution is presented to detect URDWF. Finally, a discussion is proposed on the opportunity to include new features in this part of the memory to easily distinguish between faults coming from the write driver (like URDWF) and those coming from other parts of the memory (sense amplifier, core-cells, etc.)

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously

In this paper we analyze the test power of SRAM memories and demonstrate that the full functional pre-charge activity is not necessary during test mode because of the predictable addressing sequence. We exploit this observation in order to minimize power dissipation during test by eliminating the unnecessary power consumption associated with the pre-charge activity. This is achieved through a modified pre-charge control circuitry, exploiting the first degree of freedom of March tests, which allows choosing a specific addressing sequence. The efficiency of the proposed solution is validated through extensive Spice simulations

Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or Ground Bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits with the proposed structural-based power-aware X-filling technique. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length

Non-volatile flash memories are becoming more and more popular for system-on-chip design (SoC). Embedded flash (eFlash) memories are based on the floating-gate transistor concept and can be subject to complex hard defects creating functional faults. Studies of realistic failure mechanisms and their associated fault models are the first mandatory step before providing efficient and practical new test methods. In this paper, we present an analysis made on actual failures occurring in 2T FLOTOX cells of 0.15mum NOR-based embedded flash structure

Resistive-open defects appear more and more frequently in VDSM technologies. In this paper we present a study concerning resistive-open defects in the core-cell of SRAM memories. The first target of this work is a comparison of the effect produced by resistive-open defects in the 0.13 μm and 90 nm core-cell. We show that the 90 nm core-cell is more robust than the 0.13 μm core-cell in presence of resistive-open defects. On the other hand we show that dynamic faults are most likely to occur in the 90 nm than in 0.13 μm core-cell. Finally we propose a unique March test solution that ensures the complete coverage of all the extracted fault models for both technologies.

In this paper, we present an exhaustive study on the effects of resistive-open defects in the pre-charge circuits of SRAM memories. In particular, we have analyzed the influence of resistive-opens placed in different locations of these circuits. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled with un-restored write faults (URWFs) and un-restored read faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more rentable in terms of resistive defect detection than that of URRFs.

In this paper, we present a novel study on data retention faults (DRFs) in SRAM memories. We analyze in detail the electrical origins of these faults, starting from the most common till those that lead to what we have called hard to detect DRFs. In general, DRFs are supposed to be produced by very high resistive-open defects that affect the refreshment loop of the core-cell. We demonstrate that lower values of resistance may produce hard to detect DRFs. Moreover, each resistive-open defect produces a particular faulty behavior of the core-cell that changes for different ranges of the resistive value. We analyze different cases and we propose for each one an efficient test procedure based on March tests. In particular, we propose to stimulate the defective cells in some cases by indirect accesses and in some other cases by emphasizing natural noise phenomenon of SRAM memories (such as the ground bounce).

In this paper we present an exhaustive analysis of resistive-open defect in core-cell of SRAM memories. These defects that appear more frequently in VDSM technologies induce a modification of the timing within the memory (delay faults). Among the faults induce by such resistive-open defects there are static and dynamic read destructive fault (RDF), deceptive read destructive fault (DRDF), incorrect read fault (IRF) and transition fault (TF). Each of them requires specific test conditions and different kind of March tests are needed to cover all these faults (TF, RDF, DRDF and IRF). In this paper, we show that a unique March test solution can ensure the complete coverage of all the faults induced by the resistive-open defects in the SRAM core-cells. This solution simplifies considerably the problem of delay fault testing in this part of SRAM memories.

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains according to Y. Bonhomme et al. (2003). The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.

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This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults are the consequence of resistive-open defects that appear more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.

In this paper, we propose a technique for an exhaustive testing of all the delay faults in the logic architecture of symmetrical FPGAs, in a Manufacturing-Oriented Test (MOT) context. Previous techniques, concerning the test of delay faults in an FPGA, have mainly focused on delay faults on interconnexions. Our technique enables the detection of delay faults in the logic architecture and can be viewed as a complementary approach to the previous ones. The method uses the reconfiguration property of the FPGA to make easier the test of delay faults. The configuration scheme consists in chaining the logic cells or the Look-Up Tables (LUTs) in a specific way. The chain connects each LUT output to one input of the next LUT. We demonstrate that the test of all the delay faults can be done with only two configurations and a reduced test sequence.

SUIDT (Safe User Interface Design Tool) is a model-based system that allows building interactive systems with respect to the formal semantics of functional cores. It implements a complete cooperation between task models (abstract and concrete) with both the domain model and the presentation model, while ensuring the properties of the models. Last, it maintains all during the design cycle the links between every part of the system, even the functions of the functional core (the actual code).

This paper presents a new March test solution for detection of ADOFs (Address Decoder Open Faults), and resistive-ADOFs that are the consequence of resistive-open defects in address decoders of SRAM memories. In this study, we briefly analyze the test conditions and the March test requirements for these particular faults and we introduce some modifications to the well known March C- making it able to detect ADOFs and resistive-ADOFs, without increasing its complexity and its ability to detect the former target faults. The reformulation of March C-, called March iC-, is essentially based on introducing a particular address sequence and a particular read/write data sequence. The proposed March iC- extends the ability of March-based test solutions in detecting dynamic faults in SRAM memories.

This paper presents a comparative analysis of open (ADOF: Address Decoder Open Fault) and resistive open defects in address decoders of embedded-SRAMs. Such defects are the primary target of this study because they are notoriously hard-to-detect faults. In particular, we consider dynamic defects which may appear in the transistor parallel plane of address decoders. From this study, we show that test conditions required for ADOFs testing (sensitization and observation) can be partially used also for resistive open defect testing.

Detecting delay faults in SRAM-FPGAs can be done resorting to BIST. In this context, the objective of this paper is to analyse the timing behaviour of look-up tables (LUT) contained in FPGAs in both fault-free and delay faulty cases. We first show that the propagation delay of a LUT depends both on the transition pattern applied to its inputs and on the function implemented in it. This significant result questions the use of the basic assumption - the propagation delay of a LUT is independent of the function realized by it $considered in a number of recent papers. We next demonstrate that i) some physical defects in a LUT can change its propagation delay and ii) the delay due to a timing defect within the LUT varies depending on the location of the defect. We therefore conclude that unlike what is often done in existing FPGA BIST techniques, LUTs cannot be considered as programmable black boxes during test and testing their structure, either fully or partially, is needed to guarantee complete coverage of delay faults in the FPGA.

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Power consumption during scan testing is becoming a primary concern. In this paper, we present a novel approach for scan cell ordering which significantly reduces the power consumed during scan testing. The proposed approach is based on the use of a two-step heuristic procedure that can be exploited by any chip layout program during scan flip-flops placement and routing. The proposed approach works for any conventional scan design and offers numerous advantages compared with existing low power scan techniques. Reductions of average and peak power consumption during scan testing are up to 58% and 24% respectively for experimented ISCAS benchmark circuits.

High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Input Change (RSIC) generation, that can be used to generate tests for many arbitrary misbehaviors that can occur in digital systems, thus providing a single on-chip test generation solution.

Test power is now a big concern in large system-on-chip designs. In this paper, we present a novel approach for minimizing power consumption during scan testing of integrated circuits or embedded cores. The proposed low power technique is based on a gated clock scheme for the scan path and the clock tree feeding the scan path. The idea is to reduce the clock rate on scan cells during shift operations without increasing the test time. Numerous advantages can be found in applying such a technique.

In this paper, we present a new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation. The proposed low power/energy BIST technique is based on a modified clock scheme for the TPG and the clock tree feeding the TPG. Numerous advantages can be found in applying such a technique during BIST.

A new BIST TPG design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper. When used to generate test patterns for test-per-clock BIST, it reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during testing. Moreover, the total energy consumption during BIST is also reduced since the test length produced by the mixed TPG is roughly the same as the test length produced by a classical LFSR-based TPG to reach the same fault coverage. Note that this TPG design has been developed to deal with strongly connected circuits with a small number of inputs.

Power consumption of digital systems may increase significantly during testing. In this paper, we propose a novel low power/energy Built-in Self Test (BIST) strategy based on circuit partitioning. The strategy consists of partitioning the original circuit into structural subcircuits so that each subcircuit can be successively tested through different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. The average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the subcircuits is not so far from the test length for the original circuit. The proposed strategy can be applied to either test-per-scan or test-per-clock BIST schemes by slightly modifying conventional TPG structures as illustrated in this paper. Results on ISCAS circuits show that average power reduction of up to 62%, peak power reduction of up to 57%, and energy reduction of up to 82% can be achieved at a very low area cost in terms of area overhead and with almost no penalty on the circuit timing.

We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence generator capable of reproducing the essential features of a set of precomputed deterministic test sequences. We use for this purpose two new models called hidden Markov model with patterns and independence model with patterns. Compared to existing methods, the proposed technique exhibits a very high fault coverage, including performance testing, at the expense of a low silicon area overhead.

In this paper, we propose a novel low power/energy built-in self test (BIST) strategy based on circuit partitioning. The goal of the proposed strategy is to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage. The strategy consists in partitioning the original circuit into two structural subcircuits so that each subcircuit can be successively tested through two different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. the average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the two subcircuits is roughly the same as the test length for the original circuit. Results on ISCAS circuits show that average power reduction of up to 72%, peak power reduction of up to 53%, and energy reduction of up to 84% can be achieved.

This paper considers the problem of testing VLSI integrated circuits without exceeding their power ratings during test. The proposed approach is based on the reordering of test vectors of a given test sequence to minimize the average and peak power dissipation during test operation. For this purpose, the proposed technique reduces the internal switching activity by lowering the transition density at circuit inputs. The technique considers combinational or full scan sequential circuits and do not modify the initial fault coverage. Results of experiments show reductions of the switching activity ranging from 11% to 66% during external test application.

During self-test, the switching activity of the circuit under test is significantly increased compared to normal operation and leads to an increased power consumption which often exceeds specified limits. In the first part of this paper, we propose a test vector inhibiting technique which tackles the increased activity during test operation. Next, a mixed solution based on a reseeding scheme and the vector inhibiting technique is proposed to deal with hard-to-test circuits that contain pseudo-random resistant faults. From a general point of view, the goal of these techniques is to minimize the total energy consumption during test and to allow the test at system speed in order to achieve high fault coverage. The effectiveness of the proposed low energy BIST scheme has been validated on a set of benchmarks with respect to hardware overhead and power savings.

This paper presents a new effective BIST scheme that achieves 100% fault coverage with low hardware overhead, and without any mollification of the circuit under test, i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator (e.g. an LFSR) is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very simply and with low silicon area cost, without the need of any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length.

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the serial shifting procedure. In the literature, different scan modification possibilities have been proposed for applying delay fault oriented deterministic test patterns. Another issue of the delay fault testing problem in scan-based sequential circuits is presented in this paper. The solution combines a BIST structure with the standard scan design.

With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this papel; we propose a post-mapping technique that can reduce the power dissipation by peeorming gate resizing.This technique consists of replacing some gates of the circuit with devices in a complete cell library having smaller area and, therefore, smaller gate capacitance with lower power consumption.The slack time of each gate in the circuit is first computed to determine the set of gates that can be down-sized.A global optimization procedure based on integer linear programming and the simplex method is then applied to determine the best overall gate resizing solution.Experimental results on benchmark circuits have shown a power reduction in the rangefrom 2.8 to 27.9 % compared to circuits without resizing.The most relevant features of our technique are that it is applicable to large digital circuits and gives an optimal resizing solution in a short computation time (no more than 15.8 seconds).

This paper presents a new approach for designing test sequences to be generated on-chip. The proposed technique is based on machine learning, and provides a way to generate efficient patterns to be used during BIST test pattern generation. The main idea is that test patterns detecting random pattern resistant faults are not embedded in a pseudo-random sequence as in existing techniques, but rather are used to produce relevant features allowing to generate directed random test patterns that detect random pattern resistant faults as well as easy-to-test faults. A BIST implementation that uses a classical LFSR plus a small amount of mapping logic is also proposed. Results are shown for benchmark circuits which indicate that our technique can reduce the weighted or pseudo-random test length required for a particular fault coverage. Other results are given to show the possible trade off between hardware overhead and test sequence length. An encouraging point is that results presented in this paper although they are comparable with those of existing mixed-mode techniques, have been obtained with a machine learning tool not specifically developed for BIST generation and therefore may significantly be improved.

As delay testing using external testers requires expensive equipment, built-in self-test (BIST) is an alternative technique that can significantly reduce the test cost. In this paper, a BIST test pattern generator (TPG) design for the detection of delay faults is proposed. This TPG design produces test sequences having exactly the same robust delay fault coverage as single input change (SIC) test sequences obtained with the most efficient TPGs proposed before in the literature, but with a reduced test length and less area overhead. This reduction of the test length and area overhead is obtained by determining compatible inputs of the circuit under test (CUT), i.e. inputs that can be switch simultaneously without altering the robust test coverage.

This paper presents a GA-based technique to generate diagnostic-oriented delay tests for logic circuits. The aim is to produce a test sequence for a given circuit such that any couple of non-equivalent delay faults is distinguished by at least one rest pair belonging to the test sequence. For this purpose, we decided to preferably use a simulation-based approach with a directed search mechanism rather than developing a new deterministic ATPG. An appropriate fitness function that ranks population members according to their diagnostic capabilities has been defined, and genetic operators allowing a population to evolve during successive generations are presented. In order to have a diagnostic program providing near-optimal solutions, we combined the GA-based technique proposed in this paper with an existing post test diagnostic method for delay faults. Experimental results show that the genetic approach is effective for solving our diagnostic test generation problem, and point out the fact that the GA performs very well in comparison to a random test method.

Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this paper a new test pattern generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from machine learning to generate delay fault detecting test pairs. First, a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the efficiency of our solution in terms of test sequence length and delay fault coverage.

The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first category of circuits, but not for synchronous sequential circuits. So, this paper concerns delay fault diagnosis for non-scan circuits. A preliminary version of the proposed method is first given. New concepts for allowing path tracing in the proposed diagnosis process (identification of self-masking) are also presented. As the method is based on path tracing through the sequential circuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine. Results of experiments on ISCAS-89 benchmark circuits are finally discussed.

Existing methodologies for determining delay fault coverages or for building up a delay fault dictionary are sometimes accurate, but rarely fast and easy to implement. Therefore, with the aim of removing these deficiencies, a new and more efficient fault simulation strategy for gate delay faults in combinational or scan-based circuits is presented. This method is based on a critical path tracing algorithm, thus avoiding the explicit simulation of each delay fault in the circuit. The novelty of the solution proposed to compute the detection threshold of a detectable delay fault increases the interest of the method, although it is computed approximately. Simulation results obtained for the ISCAS85 combinational benchmark circuits show the efficiency of the proposed method.>