This paper deals with the FPGA-implementation of a configurable hardware/software (HW/SW) architecture for data acquisition (DAQ) systems. The novelty of this paper is to present a HW/SW architecture which can manage most of possible applications in DAQ systems in a very flexible way meeting the performance targets. This architecture can be dynamically reconfigured and therefore adapted depending on the performance of the I/O devices. We implemented and tested our system with three representative applications for large format printers. These three applications differ in terms of sampling frequency, amount of memory and synchronization complexity. The proposed system can also be integrated in an ASIC implementation.

Two dimensional (2D) convolutions are local by nature; hence every pixel in the output image is computed using a moving window of pixels. Although the operation is simple, the hardware is conditioned by the fact that due to bandwidth efficiency full raster rows must be read from the external memory, and that a row-major image scan should be performed to support shift-variant convolutions. When extending the architectures developed in prior-art to support shift-variant convolutions, we realize that they require large amounts of on-chip memory. While this fact may not have a large cost increase in ASIC implementations, it makes FPGA implementations expensive or not feasible. In this paper, we propose several FPGA-efficient architectures for generating a moving window over a row-wise print path. Because the proposed concepts have different throughput and resource utilization, we show the most efficient based on maximizing the throughput per flip-flop count.

A power estimation tool for FPGA technology was developed. The current version is able to estimate total and individual node average power consumption in combinational blocks. The tool is statistical-based, allowing the user to specify the tolerated error for a given confidence level. Due to the fact that the power for individual nodes can be obtained, the software is able to connect this information with the physical positions of the nodes. In order to demonstrate the tool features and usability, a set of arithmetic blocks for digital radio have been utilized as benchmark circuit. Main results have been compared with actual power measurements for Virtex and Virtex-II devices.