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Ren Guo

dblp:48/7610 · DBLP profile ↗
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7ranked-venue papers
1as first author
0since 2021 · last 2020
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Graphics, computer vision, multimedia, augmented reality and games · 4 · 1 first-authorSystems, architecture and hardware · 2Software engineering, systems software and programming languages · 1Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 94% Memory systems · 6%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture
0.412020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product · ISCA 2020
Processor architecture and microarchitecture › microprocessor design
RISC-V processor
0.412020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product · ISCA 2020
Processor architecture and microarchitecture › superscalar processor
superscalar out-of-order processor
0.412020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product · ISCA 2020
Processor architecture and microarchitecture › instruction set architecture
vector extension
0.412020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product · ISCA 2020
Memory systems
cache coherence
0.112020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product · ISCA 2020
Processor architecture and microarchitecture
chip multiprocessor
0.112020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product · ISCA 2020

Methods — techniques the papers use, named apart from their topics

vector processing · 0.4out-of-order execution · 0.4multi-issue superscalar · 0.4
YearPublicationVenuePosition
2020 Xuantie-910: Innovating Cloud and Edge Computing by RISC-V
abstract
This article consists only of a collection of slides from the author's conference presentation.
Chen Chen 0058, Xiaoyan Xiang, Chang Liu 0021, Yunhai Shang, Ren Guo, Dongqi Liu 0003, Ziyi Hao, Chunqiang Li, Yu Pu, Jian-Yi Meng, Xiaolang Yan, Yuan Xie 0001, Xiaoning Qi
Hot Chips Symposium5
2020 Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product
abstract
The open source RISC-V ISA has been quickly gaining momentum. This paper presents Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it features custom extensions to arithmetic operation, bit manipulation, load and store, TLB and cache operations. It also implements the 0.7.1 stable release of RISCV vector extension specification for high efficiency vector processing. Xuantie-910 supports multi-core multi-cluster SMP with cache coherence. Each cluster contains 1 to 4 core(s) capable of booting the Linux operating system. Each single core utilizes the state-of-the-art 12-stage deep pipeline, out-of-order, multi-issue superscalar architecture, achieving a maximum clock frequency of 2.5 GHz in the typical process, voltage and temperature condition in a TSMC 12nm FinFET process technology. Each single core with the vector execution unit costs an area of 0.8 mm2, (excluding the L2 cache). The toolchain is enhanced significantly to support the vector extension and custom extensions. Through hardware and toolchain co-optimization, to date Xuantie-910 delivers the highest performance (in terms of IPC, speed, and power efficiency) for a number of industrial control flow and data computing benchmarks, when compared with its predecessors in the RISC-V family. Xuantie-910 FPGA implementation has been deployed in the data centers of Alibaba Cloud, for applicationspecific acceleration (e.g., blockchain transaction). The ASIC deployment at low-cost SoC applications, such as IoT endpoints and edge computing, is planned to facilitate Alibaba’s end-to-end and cloud-to-edge computing infrastructure.
Chen Chen 0058, Xiaoyan Xiang, Chang Liu 0021, Yunhai Shang, Ren Guo, Dongqi Liu 0003, Ziyi Hao, Chunqiang Li, Yu Pu, Jian-Yi Meng, Xiaolang Yan, Yuan Xie 0001, Xiaoning Qi
ISCA5
2015 Survey on Discrete Surface Ricci Flow
Min Zhang 0069, Wei Zeng 0002, Ren Guo, Feng Luo 0002, Xianfeng Gu
J. Comput. Sci. Technol.3
2014 The unified discrete surface Ricci flow
Min Zhang 0069, Ren Guo, Wei Zeng 0002, Feng Luo 0002, Shing-Tung Yau, Xianfeng Gu
Graph. Model.2
2013 Extremum problems for eigenvalues of discrete Laplace operators
Ren Guo
Comput. Aided Geom. Des.1
2012 Discrete heat kernel determines discrete Riemannian metric
Wei Zeng 0002, Ren Guo, Feng Luo 0002, Xianfeng Gu
Graph. Model.2
2009 Generalized Discrete Ricci Flow
abstract
Abstract Surface Ricci flow is a powerful tool to design Riemannian metrics by user defined curvatures. Discrete surface Ricci flow has been broadly applied for surface parameterization, shape analysis, and computational topology. Conventional discrete Ricci flow has limitations. For meshes with low quality triangulations, if high conformality is required, the flow may get stuck at the local optimum of the Ricci energy. If convergence to the global optimum is enforced, the conformality may be sacrificed. This work introduces a novel method to generalize the traditional discrete Ricci flow. The generalized Ricci flow is more flexible, more robust and conformal for meshes with low quality triangulations. Conventional method is based on circle packing, which requires two circles on an edge intersect each other at an acute angle. Generalized method allows the two circles either intersect or separate from each other. This greatly improves the flexibility and robustness of the method. Furthermore, the generalized Ricci flow preserves the convexity of the Ricci energy, this ensures the uniqueness of the global optimum. Therefore the algorithm won't get stuck at the local optimum. Generalized discrete Ricci flow algorithms are explained in details for triangle meshes with both Euclidean and hyperbolic background geometries. Its advantages are demonstrated by theoretic proofs and practical applications in graphics, especially surface parameterization.
Yongliang Yang 0002, Ren Guo, Feng Luo 0002, Shi-Min Hu 0001, Xianfeng Gu
Comput. Graph. Forum2