This paper presents the approach to design the inverter based CTLE at the minimum power consumption point and at minimum noise power product point while meeting the desired specification target. Lagrangian function for constrained optimization is formed. Mathematical close form expressions of the CTLE parameters are derived. Using the proposed design approach, an inverter based CTLE architecture with four different design constraints was designed and simulated in 16nm FinFET and in 65nm CMOS technology to validate existence of minimum power point design.

For given simple graphs $G_1$ and $G_2$, the size Ramsey number $\hat{R}(G_1,G_2)$ is the smallest positive integer $m$, where there exists a graph $G$ with $m$ edges such that in any edge coloring of $G$ with two colors red and blue, there is either a red copy of $G_1$ or a blue copy of $G_2$. In 1981, Erdös and Faudree investigated the size Ramsey number $\hat{R}(K_n,tK_2)$, where $K_n$ is a complete graph on $n$ vertices and $tK_2$ is a matching of size $t$. They obtained the value of $\hat{R}(K_n,tK_2)$ when $n\geq 4t-1$ as well as for $t=2$ and asked for the behavior of these numbers when $t$ is much larger than $n$. In this regard, they posed the following interesting question: For every positive integer $n$, is it true that $\lim_{t\to \infty} ({\hat{R}(K_n,tK_2)}/{t\, \hat{R}(K_n,K_2)})= \min\{\binom{n+2t-2}{2}/ {t\binom{n}{2}}\mid t\in \mathbb{N}\}?$ In this paper, we obtain the exact value of $\hat{R}(K_n,tK_2)$ for every pair of positive integers $ n,t$, and as a byproduct, we give an affirmative answer to the question of Erdös and Faudree.