Matrix inversion for real-time applications can be a challenge for the designers since its computational complexity is typically cubic. Parallelism has been widely exploited to reduce such complexity, however most traditional methods do not scale well with the matrix size leading to communication bottlenecks. In this paper we exploit a decentralised parallel hardware architecture based on a strongly non-singular matrix inversion algorithm proposed by Kant and Kimura in 1978, which is a parallel-orientated method with communication mode independent of the matrix size, mitigating the problem of matrix scalability. The hardware architecture is implemented in two different approaches using fixed-point arithmetic: dedicated and shared. In the first approach a matrix can be inverted in linear time while the latter, for the best case, has a square complexity. Experimental results are demonstrated using a Stratix V GX FPGA. For instance, in dedicated approach an 8x8 matrix is inverted in 1.27us, while in shared approach a 64x64 matrix is inverted in 153.40us using 64 pipelined processing elements.

We have compared two different resource arbitration architectures in our developed data acquisition and stimuli generator system for neuroscience research, entirely specified in a high-level Hardware Description Language (HDL). One of them was designed with a decoupled and latency insensitive modular approach, allowing for easier code reuse, while the other adopted a centralized scheme, constructed specifically for our application. The usage of a high-level HDL allowed straightforward and stepwise code modifications to transform one architecture into the other. Despite the logic complexity penalty of synthesizing our hardware from a highly abstract language, both architectures were implemented in a very small programmable logic device without even consuming all the hardware resources. While the decoupled design has shown more resilience to input activity bursts, the centralized one gave an economy of about 10-15% in the device logic element usage. This system is not only useful for neuroscience protocols that require timing determinism and synchronous stimuli generation, but has also demonstrated that high-level languages can be effectively used for synthesizing hardware in small programmable devices.