Steady-state temperature due to Joule self-heating for highly coupled integrated-circuit interconnect can be found rapidly on individual interconnect segments during electromigration reliability verification. It has previously been shown that the dc electric current solution on each interconnect segment of a net may be modified to form the analytical solution of the 1-D time-independent heat equation along the entire net. A symbolic solution of the network equations (requiring O(P3) operations, where P is the number of nodes) is first evaluated to solve the electrical problem and then evaluated again to solve the resulting Joule heat problem (each evaluation requiring O(P) operations). The symbolic solution is extended here to couple each interconnect segment to the weighted average temperature of the segments on neighboring nets. The temperature over the entire set of nets may be found by iterating until convergence, which does not require a significant overall increase in operations. The accuracy of the temperature trajectories is principally dependent on the validity of the assumptions that the temperature background seen by each individual interconnect segment is uniform and that vias conduct heat only along their lengths. The estimated temperature of self-heated nets is 110% of the finite-element result for a realistic layout example. The net-based solution is well suited to distributed processing and identifying problematic layout.

Full-chip capacitance extraction programs based on lookup techniques, such as HILEX/CUP , can be enhanced to rigorously account for process variations in the dimensions of very large scale integration interconnect wires with only modest additional computational effort. HILEX/CUP extracts interconnect capacitance from layout using analytical models with reasonable accuracy. These extracted capacitances are strictly valid only for the nominal interconnect dimensions; the networked nature of capacitive relationships in dense, complex interconnect structures precludes simple extrapolations of capacitance with dimensional changes. However, the derivatives, with respect to linewidth variation of the analytical models, can be accumulated along with the capacitance itself for each interacting pair of nodes. A numerically computed derivative with respect to metal and dielectric layer thickness variation can also be accumulated. Each node pair's extracted capacitance and its gradient with respect to linewidth and thickness variation on each metal and dielectric layer can be stored in a file. Thus, instead of storing a scalar value for each extracted capacitance, a vector of 3I+1 values will be stored for capacitance and its gradient, where I is the number of metal layers. Subsequently, this gradient information can be used during circuit simulation in conjunction with any arbitrary vector of interconnect process variations to perform sensitivity analysis of circuit performance.