With increasing demands of virtual reality (VR) applications, efficient VR rendering techniques are becoming essential. Because VR stereo rendering has increased computational costs to separately render views for the left and right eyes, to reduce the rendering cost in VR applications, we present a novel traversal order for tile-based mobile GPU architectures: Z 2 traversal order. In tile-based mobile GPU architectures, a tile traversal order that maximizes spatial locality can increase GPU cache efficiency. For VR applications, our approach improves upon the traditional Z order curve. We render corresponding screen tiles in left and right views in turn, or simultaneously, and as a result, we can exploit spatial adjacency of the two tiles. To evaluate our approach, we conducted a trace-driven hardware simulation using Mesa and a hardware simulator. Our experimental results show that Z 2 traversal order can reduce external memory bandwidth requirements and increase rendering performance.

When designing an SoC (system-on-chip), one should ensure that the chip's architecture delivers optimal data throughput for high-speed connectivity blocks on practical use, taking of several layers of software into account. Previous works such as simulation based estimation method or analytical method that focused on estimation of low level throughput in link layer are not adequate for accurately estimating throughput of the real silicon SoC because practical use cases of such complex connectivity blocks typically require extensive software operation on top of platform operating systems like Linux. FPGA-based emulation, therefore, is commonly used to verify functional correctness of complex connectivity blocks in a more realistic usage scenario with real connectivity devices like USB 2.0 mass storage devices. Speed of FPGA emulation, though, is scaled down significantly because of inherent limitation of FPGA emulation while speed of interface to real connectivity devices is required to be at-speed for compliance with connectivity specification standards. For this reason, scaling factors of speed are not uniform and, thus, measurement of performance is not accurate. This paper proposes a method to compensate errors due to the non-uniform scaling factors. In the proposed method, measurements of various parameters in FPGA emulation are applied to a high-accuracy estimation model that we created. Our method was applied to USB2.0, and the experimental result shows 4.1% of estimation error.

A transaction level modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented the transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model is shown to be 353 times faster than the pin-accurate RTL model, while maintaining 97% accuracy on average. We also present the TLM development procedure of a bus architecture.

For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an SoC design. Furthermore, bus IP vendors provide software tools that automatically generate RTL codes of a bus once its designer configures it. Configurability, however, imposes more challenges upon designers because complexity involved in optimization increases exponentially as the number of parameters grows. In this paper, we present a novel approach with which effort requirement can be dramatically reduced. An automated optimization tool we developed is used and it exploits a genetic algorithm for fast design exploration. This paper shows that the time for the optimizing task can be reduced by more than 90% when the tool is used and, more significantly the task can be done without an expert's hand while ending up with a better solution.