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Wenjuan Zhu 0002

dblp:49/1641-2 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2018
0000-0003-2824-1386ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 30% Energy-efficient computing · 30% Integrated circuit design · 30%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › low-power design
low-power processor design
0.312018
HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs · ISCA 2018
Integrated circuit design › emerging device technologies
tunneling field effect transistor
0.312018
HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs · ISCA 2018
GPUs and heterogeneous computing
GPU architecture
0.112018
HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs · ISCA 2018

Methods — techniques the papers use, named apart from their topics

simulation · 0.3
YearPublicationVenuePosition
2018 HetCore: TFET-CMOS Hetero-Device Architecture for CPUs and GPUs
abstract
Tunneling Field-Effect Transistors (TFETs) attain much higher energy efficiency than CMOS at low voltages. However, their performance saturates at high voltages and, therefore, cannot replace CMOS when high performance is needed. Ideally, we desire a core that is as energy-efficient as a TFET core and provides as much performance as a CMOS core. To approach this goal, this paper judiciously integrates both TFET units and CMOS units in a single core, effectively creating a hetero-device core. We call it HetCore, and present CPU and GPU versions. In HetCore, TFETs are used in units that consume high power under CMOS, are amenable to pipelining or are not very latency sensitive, and use a sizable area. HetCore powers CMOS and TFET units at different voltage levels, so they operate optimally. However, all units are clocked at the same frequency. Our results based on simulations running standard applications show the potential of this approach, even with conservative assumptions. A HetCore CPU consumes on average 39% less energy than a CMOS CPU, while delivering an average performance that is within 10% of the CMOS CPU. In addition, under a fixed power budget, a multicore with HetCore CPUs can employ twice as many cores as a multicore with CMOS CPUs, resulting in average performance gains of 32% while, at the same time, improving the energy efficiency (ED2) by an average of 68%. Similar results are obtained with HetCore GPUs.
Bhargava Gopireddy, Dimitrios Skarlatos 0002, Wenjuan Zhu 0002, Josep Torrellas
ISCA3