The number theoretic transform (NTT) and its inverse (INTT) are efficient mathematical tools for polynomial multiplication, making them highly suitable for cryptographic applications such as image encryption and decryption. This work presents novel hardware architectures for NTT and INTT, designed explicitly for energy-efficient image encryption. Our primary contributions include the introduction of an approximate radix-2mlogarithm (AxRLL-16) based on a leading one detector (LOD) and Radix-16 encoder, which optimizes modular reduction operations by significantly reducing computational complexity. The NTT and INTT proposals are synthesized under a 65nm technology and achieve substantial improvements in power, area, and energy efficiency. Compared to state-of-the-art designs, our NTT and INTT implementations exhibit over 96.13% areasavings and 96.88% power-savings, with energy consumption reduced by up to 207 times.

This work proposes an integrated framework for accuracy and logic synthesis (LS) estimation of approximate adders (FALSAx). It represents a versatile and robust framework designed to estimate the accuracy, power, and area of various approximate adders (AxAs) for any input width (W) and K bits of approximation using machine learning (ML) models. FALSAx facilitates performance predictions and optimization for different AxAs configurations through meticulously curated datasets and ML-driven analysis. The framework’s capability to automatically generate Pareto fronts from estimated values aids in identifying optimal trade-offs among crucial metrics, providing essential insights for circuit design and optimization. The FALSAx includes four internal frameworks: FrAQ, PILSE, and FELSE, which estimates dynamic power, total leakage power, and area, with frequency variations automatically, and the FALED dataset of the FALSAx. As a case study, this work analyzed 16 types of AxAs on FALSAx: AMA-V, AxPPA, COPY, TRUNC, ETA, LOA, HOERAA, LDCA, LZTA, HEAA, M-HEAA, HERLOA, M-HERLOA, HOAANED, OLOCA, and SETA. The rigorous analysis provided by FALSAx revealed that HERLOA, M-HERLOA, M-HEAA, and AxPPA demonstrated superior accuracy metrics such as SSIM, NCC, MAE, and MRE. Furthermore, power analysis showed that AxPPA exhibited the best power efficiency for lower approximation bits ($K \leq 3$). At the same time, gate-free adders like COPY, TRUNC, AMA-V, LDCA, and LZTA were more power-efficient for higher approximation bits ($K \gt 3$). Area estimations indicated that AxPPA maintained competitive efficiency for lower approximation bits ($K \leq 5$), while TRUNC and LDCA were more efficient for higher bits ($K \gt 5$).

Alfaba, presented in this paper, is a low-cost, multi-sensory educational tool tailored to enhance literacy in underprivileged children. It leverages neuroplasticity principles, employing a tactile, interactive approach to develop essential neural connections for reading and writing. Tested with 11 children aged 7 to 10 years, its usability evaluation demonstrated effectiveness and user-friendliness, particularly in socially vulnerable contexts. Its cost-effectiveness makes Alfaba accessible in resource-limited settings, aiming to reduce educational disparities. Alfaba's innovative design focuses on providing equal learning opportunities for all children, regardless of socioeconomic background, making it a significant step toward educational equity and demonstrating the inclusive integration of technology in education for widespread impact.

Transactional Causal Consistency (TCC) is the strongest consistency model compatible with availability and, therefore, it avoids the pitfalls of the CAP theorem while simplifying the programming of cloud applications. Unfortunately, with previous implementations, TCC came at the cost of expensive reads. TCC has been implemented either using conservative approaches, that always require two communication rounds, or using optimistic approaches that, in good cases, require just one round, but in face of skewed workloads, that are common in real applications, can require three communication rounds. In this paper we propose a novel algorithm, named PrompTCC, that in most cases offers reads in just one round and that, even in face of skewed workloads, never takes more than two rounds. As a result, PrompTCC is able to closely approximate the performance of an eventually consistent system while providing stronger guarantees, achieving only 12% throughput and 20% latency penalty in realistic scenarios, outperforming state-of-the-art systems which present up to 37% and 60% throughput and latency degradation respectively.

Approximate computing maximizes area and energy savings for a trade-off between quality and efficiency. Approximate arithmetic operators have emerged as an efficient alternative to design low-power VLSI circuits. This paper investigates the design of approximate arithmetic operator units used in the calibration procedure for radio astronomy light sensors — the so-called StEFCal (statistically efficient and fast calibration) method. The StEFCal algorithm comprises arithmetic operations like a divider, square-accumulate (SAC), and multiply-accumulate (MAC) units. The StEFCal circuit of this work explores the following arithmetic operators: i) two approximate squarer units from the literature, i.e., radix-4 (AxRSU) and SquASH, ii) two approximate iterative-based Newton-Raphson (NR) and Goldschmidt (GLD) dividers, iii) one approximate parallel prefix adder (AxPPA), and iv) a new approximate radix-4 multiplier (AxRMU), proposed in this work, explored in the StEFCal multiply-accumulate circuit design. The AxRSU utilizes the parameters$K1$and$K2$to represent the number of exact encoders for squarer- and conventional-partial products, respectively, subsequently replaced with approximate encoders. The same principle applies to AxRMU, where the parameter$K$indicates the number of exact encoders for conventional-partial products, subsequently exchanged with approximate encoders. We demonstrate the efficiency of StEFCal using the approximate arithmetic operators from the Pareto-optimal front that expresses the area- and power-quality trade-off. The results show that using the AxRSU with$K1=4$and$K2=6$, AxRMU, and AxPPA with$K=16$and NR with one iteration has an MSE equal to 89.98dB and offers up to$158\times $energy-savings compared to the exact StEFCal, and up to$25\times $more energy-savings and$3.33\times $area-savings compared with our previous work,$440\times $energy-savings compared to the accurate state-of-the-art, and$258\times $compared with the approximate state-of-the-art.

The Covid-19 pandemic has driven students out of schools around the world. In Brazil, a developing country, this dropout has damaged the literacy of students between the ages of 5 and 9. We are running against the clock, and solutions to develop skills to promote reading and writing are fundamental. For students with learning difficulties, the damage is even greater. Dyslexic students have difficulties that naturally make this step even more complex for them. This work presents Alfaba: a tangible solution developed with low-cost hardware that stimulates literacy skills. Alfaba got evaluated by professionals and teachers and prototyped to support not just dyslexic students, but every student that needs to be supported at this stage of their learning journey. Our results show that Alfaba meets the needs of students and that its functions are consistent with the skills to be worked on in the reading and writing process.

Addition units are widely used in many computational kernels of several error-tolerant applications such as machine learning and signal, image, and video processing. Besides their use as stand-alone, additions are essential building blocks for other math operations such as subtraction, comparison, multiplication, squaring, and division. The parallel prefix adders (PPAs) is among the fastest adders. It represents a parallel prefix graph consisting of the carry operator nodes, called prefix operators (POs). The PPAs, in particular, are among the fastest adders because they optimize the parallelization of the carry generation ($G$) and propagation ($P$). In this work, we introduce approximate PPAs (AxPPAs) by exploiting approximations in the POs. To evaluate our proposal for approximate POs (AxPOs), we generate the following AxPPAs, consisting of a set of four PPAs: approximate Brent–Kung (AxPPA-BK), approximate Kogge–Stone (AxPPA-KS), Ladner-Fischer (AxPPA-LF), and Sklansky (AxPPA-SK). We compare four AxPPA architectures with energy-efficient approximate adders (AxAs) [i.e., Copy, error-tolerant adder I (ETAI), lower-part OR adder (LOA), and Truncation (trunc)]. We tested them generically in stand-alone cases and embedded them in two important signal processing application kernels: a sum of squared differences (SSDs) video accelerator and a finite impulse response (FIR) filter kernel. The AxPPA-LF provides a new Pareto front in both energy-quality and area-quality results compared to state-of-the-art energy-efficient AxAs.

The current prevalence of the internet for secret communication, alongside the development of the Internet of Things (IoT), increases the importance of cryptography for information security. Considering that the most widely shared archives are images and that traditional encryption algorithms, such as the Advanced Encryption Standard (AES), are not optimized for image encryption, researchers have investigated the use of chaos theory in image encryption schemes. However, their elevated encryption time and memory access, due to the number of scannings needed to cipher an image, have been an issue for chaotic ciphers. Considering this, a new cipher is proposed in this work in which the plain-image is divided into blocks and a simultaneous permutation-diffusion is adopted, increasing the cipher's time efficiency. The cipher is executed in a Raspberry Pi 3 device, and it presents a significant increase in throughput compared to other similar works in literature. Additionally, extensive security evaluations showed that the cipher is secure relative to statistical, differential, chosen-plaintext, brute force, noise, and occlusion attacks, which are hence suitable for the application in real-time IoT applications.

The technology scaling has boosted the importance and gravity of radiation faults. Hardening techniques are required to ensure a high level of reliability, mainly to the harsh critical applications. Hardware redundancy remains the most adopted option to deal with fault tolerance, mostly the TMR technique. However, the weakness of this technique is the voter circuit. This paper investigates the robustness of nineteen majority voter designs in the presence of a SET. The analysis explores critical diffusion areas and LET threshold. The results show designs with 3X difference in the number of critical diffusion areas and 6X in the LET threshold.

Approximate computing emerged as a design alternative to boost design efficiency by leveraging the intrinsic error resiliency of many applications. Several error-resilient and compute-intensive applications such as signal, image, and video processing, computer vision, and supervised machine learning perform mean squared error (MSE) estimation during the runtime demanding dedicated squarer logic units in their hardware accelerators. This work proposes an approximate Radix-4 squarer unit architecture (AxRSU). Our AxRSU proposal reduces the encoder complexity and the number of required partial products, which considerably boosts energy and circuit area savings. We demonstrate the AxRSU error-quality trade-off in an SSD (Sum Squared Difference) hardware accelerator as a case study targeting a video processing application. We offer a new Pareto front with eighth optimal AxRSU solutions ranging 52-97% of cross-correlation (i.e., accuracy) for savings of 15-47% in energy consumption and 12-32% in circuit area.

Bias Temperature Instability (BTI) is a central issue in integrated circuits' reliability, as it degrades transistors' performance. In deeply scaled technologies, an increasing variability accompanies this effect. Secure topologies for cryptographic circuits aiming to increase resilience to Side-Channel Attacks through a homogeneous power consumption may be particularly subject to the impact of an unbalance caused by an aging effect. A statistical evaluation based on Monte Carlo simulations with a time-dependent BTI model based on trap kinetics was performed in this work. The results indicate that, despite the significant variability and degradation caused by the BTI in the secure cells' performance, the homogeneity of the power consumption was not considerably affected.

Secure triple track logic (STTL) is a circuit-level countermeasure to differential power analysis (DPA) attacks based on dual-rail precharge logic (DPL). STTL is robust to attacks due to the delay insensitive topology characteristic that avoids the glitches generated by the different path delays, before the logic gate inputs stabilize. However, the main STTL drawbacks are the validation of timing-robustness and the unbalanced and asymmetric transistors arrangement that result in variable internal capacitances and different internal paths to the current flow behaviors. The main contribution of this work is a new STTL-based topology called MT-BSTTL that combines multi-threshold with a set of circuit balancing improvements on capacitance, current paths, and fan-in, aiming to maximize the energy-efficiency while still preserving the side-channel attack-resistance. Three basic logic gates were implemented using the proposed strategy and other secure transistor topologies, all using the TSMC 40 nm technology. Results show that MT-BSTTL outperforms all state-of-the-art logic styles in terms of robustness against DPA attacks. Comparing to the baseline STTL, the proposed MT-BSTTL is, at least, 50% faster, has 53.5% higher energy-efficient, and it is 44% more robust, incurring in a 40% circuit area penalty.

Differential power analysis (DPA) and differential electromagnetic analysis (DEMA) are powerful type of attack enabled to discover confidential information processed on cryptosystems. These attacks are very sensitive to temporal desynchronization of processing caused by countermeasures. DPA based on energy calculation to realign traces is a solution found in the literature. However, in those proposals, the complete trace must be processed and issues such as the number of samples in the segment used to calculate energy traces and its effects on the attack are not discussed. This paper proposes an attack flow able to realign traces disturbed by random frequency and time shift countermeasures based on three steps: signature extraction, subsampling and energy calculation. This proposal evaluates the suitable segment length to improve the efficiency of the DEMA attack applied to a hardware implementation of the DES (Data Encryption Standard) algorithm prototyped in FPGA. Results highlight a reduction of up to 93.69% in the number of traces required for a successful attack when segments are sized to approximately half the clock cycle of the cryptosystem operating frequency.

Public Software can be defined as any software that is endorsed by a Public Agent and distributed for wide use by the society. The concept of Public Software is an outspread of the idea that "software" is an important asset for the welfare of society, and therefore providing citizens with proper software tools is a task of public interest, which in some cases should be performed by the government itself. When a Public Agent endorses a software and gives it the "seal" of Public Software, he is -- explicitly or implicitly -- declaring that such software complies with minimum technical requirements, and stimulates its wide use by the society In the present paper, we discuss the importance that such requirements encompasses Information Security and we propose a validation model that is strongly based on security evaluation. In a world where cyber-crime is a reality and cyber-war becomes more and more relevant, it is fundamental that the Public Agent verify the Information Security aspects of a software before declaring it a Public Software, for otherwise, this Public Agent can be stimulating that security flaws and vulnerabilities are spread in the society, possibly in critical applications. We additionally discuss the importance of a strong validation procedure to assure the appropriate behavior of software regarding its functionalities and Information Security aspects. We conclude describing the Brazilian experience with the "Brazilian Public Software Portal" Public Software repository of open-source software.

Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind triple rail logic are valid and may provide interesting design guidelines to get DPA resistant circuits which are also more robust against DEMA.

Building fully synchronous VLSI circuits is becoming less viable as circuit geometries evolve. However, before the adoption of purely asynchronous strategies in VLSI design, globally asynchronous, locally synchronous (GALS) design approaches should take over. The design of circuits using complex field programmable components like state of the art FPGAs follows this same trend. In GALS design, a critical step is the definition of asynchronous interfaces between synchronous regions. This paper proposes SCAFFI, a new asynchronous interface to interconnect modules inside FPGAs. The interface is based on clock stretching techniques to avoid metastability. Differently from other interfaces, it can use both logic levels for stretching and do not require the use of arbiters. Also, compactness of the implementation is enhanced by the use of dedicated FPGA hard macros. A GALS version implementation of an RSA cryptography core demonstrates the use of SCAFFI.