Abstract We present the Cooperating Proof Calculus (CPC), an evolving set of proof rules encompassing all inferences used in the mainstream theories of the SMT solver cvc5. CPC consists of 585 proof rules, which are formalized in 8025 lines of definitions in the logical framework Eunoia. Eunoia proofs are independently checkable by the proof checker Ethos. This paper gives a detailed summary of CPC, surveying its proof rules over its major components. Having instrumented cvc5 to generate CPC proofs in Eunoia, we show that the solver is capable of generating fine-grained CPC proofs, with no proof holes, for all benchmarks in the SMT library except those in logics with floating-point arithmetic, which are currently not supported. This results in more than 900 million proof steps using 427 unique proof rules. We also discuss ongoing work in the proof assistants Lean and Isabelle to verify the correctness of CPC.

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The Forte formal verification environment for datapath-dominated hardware is described. Forte has proven to be effective in large-scale industrial trials and combines an efficient linear-time logic model-checking algorithm, namely the symbolic trajectory evaluation (STE), with lightweight theorem proving in higher-order logic. These are tightly integrated in a general-purpose functional programming language, which both allows the system to be easily customized and at the same time serves as a specification language. The design philosophy behind Forte is presented and the elements of the verification methodology that make it effective in practice are also described.

Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating internal state such as the program counter; floating-point circuits perform divide and square root computations iteratively. Iterative algorithms often have complex implementations because of performance optimizations like result speculation, re-timing and circuit redundancies. Verifying these iterative circuits against high-level specifications requires two steps: reasoning about the algorithm itself and verifying the implementation against the algorithm. In this paper we discuss the verification of four iterative circuits from Intel microprocessor designs. These verifications were performed using Forte, a custom-built verification system; we discuss the Forte features necessary for our approach. Finally, we discuss how we maintained these proofs in the face of evolving design implementations.

We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification.The constraints are used to decompose verifications by sets of case splits and to restrict verifications by validity conditions.Our technique is applicable to any symbolic simulator.We illustrate our technique on state-of-the-art Intel (R) designs, without removing latches or modifying the circuits in any way.

We describe the verification of the IM: a large, complex (12,000gates and 1100 latches) circuit that detects and marks the boundariesbetween Intel architecture (IA-32) instructions. We verified agate-level model of the IM against an implementation-independentspecification of IA-32 instruction lengths. We used theorem provingto to derive 56 model-checking runs and to verify that the model-checkingruns imply that the IM meets the specification for all possiblesequences of IA-32 instructions. Our verification discoveredeight previously unknown bugs.

We describe an efficient validity checker for the quantifier-free logic of equality with uninterpreted functions. This logic is well suited for verifying microprocessor control circuitry since it allows the abstraction of datapath values and operations. Our validity checker uses special data structures to speed up case splitting, and powerful heuristics to reduce the number of case splits needed. In addition, we present experimental results and show that this implementation has enabled the automatic verification of an actual high-level microprocessor description.

The DFT (DOCUMENT, FIND, THESEUS) online documentation system resembles other hypertext software in managing a full-text database with reference links (pointers) between passages (nodes). But DFT's prime role as an end-user reference service at a computer center where text updates are frequent required extra access methods often neglected in hypertext systems. To solve the problem of rapid, high-recall search for specific answer passages we combined syntactical interface features (substring and fuzzy matching of search terms) with a semantic expansion of the system's entry vocabulary. Extensive aliasing increased the number of descriptions under which any passage could be found. Conversion of the NBS GAMS classification scheme for mathematical software into descriptors allowed us to impose a virtual organization on our subroutine documentation that supports easy, task-oriented retrieval without tedious path walking. To solve the problem of reliable database maintenance amid frequent passage revisions we developed software tools for flexible input of text and entry-term changes, as well as for thorough and versatile status reporting. These, together with special features for testing and privately simulating changes and for coordinating the sequence of text and entry-term updates for maximum efficiency, yielded a robust and practical answer-delivery system. © 1991 John Wiley & Sons, Inc.