We propose an easy-to-implement hard-decision majority-logic decoding algorithm for Reed-Muller codes RM(r,m) with m ≥ 3, m/2 ≥ r ≥ 1. The presented algorithm outperforms the best known majority-logic decoding algorithms and offers highly parallel decoding. The result is of special importance for safety- and time-critical applications in embedded systems. A simple combinational circuit can perform the proposed decoding. In particular, we show how our decoder for the three-error-correcting code RM(2, 5) of dimension 16 and length 32 can be realized on hardware level.

Short-length Reed-Muller codes under majority-logic decoding are of particular importance for efficient hardware implementations in real-time and embedded systems. This paper significantly improves Chen's two-step majority-logic decoding method for binary Reed-Muller codes RM(r,m), r ≤ m/2, if - systematic encoding assumed - only errors at information positions are to be corrected. Some general results on the minimal number of majority gates are presented that are particularly good for short codes. Specifically, with its importance in applications as a 3-error-correcting, self-dual code, the smallest non-trivial example, RM(2,5) of dimension 16 and length 32, is investigated in detail. Further, the decoding complexity of our procedure is compared with that of Chen's decoding algorithm for various Reed-Muller codes up to length 210.