International audience

This article explores a low-cost solution for generating modulated test stimuli using a standard digital automated test equipment (ATE). The technique relies on the generation of a modulated binary signal with appropriate encoding using a digital tester channel and the exploitation of one of its harmonic replicas. A theoretical analysis is presented in this article, considering a simple modulation scheme, i.e., the single-tone frequency or phase modulation. The relationship between the baseband spectrum and the harmonic replicas is established and an analytical expression of the modulated digital signal is derived, taking into account effects associated with discrete-time generation. A corruption estimator is then defined, enabling nondestructive sampling conditions to be identified. Experimental results are provided demonstrating the ability of the proposed solution to generate a modulated signal with the desired characteristics at a frequency higher than that of the test equipment.

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. However, its susceptibility to defects increases due to the complexity of the process fabrications and smaller feature sizes. This article proposes compact and low-cost analytical models to evaluate the delay increase in FinFET-based circuits due to resistive open defects. The models rely on electrical simulations to precharacterize the circuit library. Analytical expressions are developed for the three types of resistive opens that may occur in FinFET-based logic cells using multifin and multifinger structures. These types of resistive opens include: a resistive open at the drain or source of the transistors (RODS), a resistive open affecting the gate of a single transistor, and a resistive open affecting the gates of both nMOS and pMOS transistors. Compact analytical models are also developed to evaluate the delay increase due to the resistive open defects under process variations. Independent and correlated process variations are taken into account. The analytical models have been validated against SPICE electrical simulations. The proposed analytical models can be used to evaluate the detectability of resistive open defects, significantly reducing the cost of dealing with different defect sizes. Potential applications of the developed analytical models are delineated. This work allows us to have higher quality and reliable electronic products.

This paper targets reduction of RF testing costs, focusing in particular on the generation of modulated stimuli for testing the reception chain of RF communication devices. It proposes an innovative low-cost solution that can be implemented on a standard digital Automated Test Equipment (ATE). The approach relies on the generation of a baseband digital signal with specific encoding, and the exploitation of one of its harmonic replicas as RF test stimulus. Spectral integrity of the signal around the targeted harmonic replica is ensured through a careful selection of the ATE sampling frequency. A generic methodology for practical implementation is presented and illustrated in this paper considering two popular digital modulation formats, namely Binary Phase-Shift Keying (BPSK) and Minimum-Shift Keying (MSK). Experimental validation is performed using a microcontroller unit (MCU) capable of operating at a sampling rate up to 500Mbps. Results show that despite the limited sampling capability of the equipment, test stimuli with the desired spectral characteristics in the 433MHz and 868MHz ISM bands can be generated, validating the proposed solution.

International audience

In this paper, we explore a digital-based solution for the generation of 2.4GHz OSQSK test stimuli. The objective is to reduce the testing costs of ZigBee receivers by enabling their test on a standard digital Automatic Test Equipment (ATE). The proposed strategy relies on the generation of a modulated square wave signal in the intermediate frequency band using a digital tester channel, and the filtering of one of its harmonics to produce the RF signal. Appropriate modulation format has to be encoded in the square-wave signal so that the typical characteristics of a ZigBee signal are present in the chosen harmonic component. A dedicated pre-processing algorithm has been developed to determine this encoding. The proposed strategy is then evaluated through Matlab simulations, taking into account the practical constraints imposed by a standard digital ATE.

Error vector magnitude (EVM) or alternately offset EVM (OEVM) is one of the most important performance to verify for RF circuits, such as ZigBee transmitters in order to ensure that the quality of the generated modulated signal complies with the requirements of the wireless communication standard. The conventional solution to measure this performance relies on the use of an automatic test equipment (ATE) equipped with expensive RF channels. This article presents a low-cost solution that permits to realize EVM measurement using only a standard digital ATE. The approach is based on 1-bit undersampled acquisition of the RF modulated signal by a digital tester channel associated with a specifically tailored processing algorithm. This algorithm involves many different steps that are detailed in this article, including phase and amplitude fluctuation extraction, RF signal reconstruction, symbol clock recovery, symbol bits detection, and synthesis of reference data for EVM calculation. The proposed digital test solution is first evaluated through lab hardware experiments and then validated with EVM measurements on an industrial ATE.

Systems on a chip have seen their surface area increased by a factor of 10 and their consumption multiplied by 5 during the last ten years. Each technological node that enabled this integration has also added new constraints challenging the overall system reliability. In addition, the integration of analog/RF blocks adds specific issues, in particular the high cost of the required test equipment. It is therefore necessary to improve test and reliability solutions in order to guarantee the production yield and the system life-time. Moreover, the massive increase in the use of communicating systems has introduced security as a cornerstone of their development. The entire hardware production flow is therefore subject to security and trust issues requiring the development of dedicated test solutions. In this paper, we focus on LIRMM contributions in the HADES project especially with details on Embedded Test Instruments (ETIs) for reliability of digital ICs, low-cost RF test based on indirect DC measurements or digital ATE capture, management of secure scan access.

This paper presents a low-cost solution to perform power and spectral measurements on RF signals. More specifically, we target RF modulated signals such as 2.4 GHz signals delivered by ZigBee transmitters. The solution is based on 1-bit under-sampled acquisition of the RF signal, acquisition that can be realized using a standard digital ATE channel. The captured binary sequence is then fed to a dedicated postprocessing algorithm, which (i) extracts amplitude and phase variations and (ii) reconstructs the RF signal. From the reconstructed signal, it is possible to perform power and spectral measurements. The different steps of the post-processing algorithm are detailed in the paper. The validity of the technique is demonstrated through both simulations and hardware measurements.

This paper presents a low-cost solution to implement a functional test for RF ZigBee transmitter. More precisely, the objective is to enable symbol error detection for a 2.4 GHz OQPSK-modulated signal with half sine pulse shaping on a digital ATE. The test is based on 1-bit under-sampled acquisition ofthe RF signal with a standard digital tester channel. A dedicated post-processing algorithm is then applied, which (i) extracts the phase information from the captured binary sequence, (ii) reconstructs the RF modulated signal and (iii) performs the demodulation. The different steps ofthe post-processing algorithm are detailed in this paper. Simulation and experimental results are presented, demonstrating the ability of the technique to correctly retrieve the emitted symbol sequence using only the binary data captured by the digital tester channel.

This paper presents a comprehensive study towards the identification and quantification of the detectability improvement of resistive open and short defects, brought by specific supply voltage and body biasing conditions applied during manufacturing test. The study is conducted using a didactic circuit implemented in 28nm UTBB FDSOI-RVT (Ultra-Thin Body and Buried oxide Fully Depleted Silicon-On-Insulator, Regular VT) technology in the context of delay-based test. Electrical simulation results are analyzed in order to both highlight the optimal test conditions overall and evaluate the individual improvement in defect detection brought by each factor (supply voltage and body biasing conditions), for different resistive defect types.

This paper presents an embedded test instrument for on-chip phase noise evaluation of analog/IF signals. The technique relies on 1 -- bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. The module is validated through behavioral and structural simulations. Its implementation in CMOS 140nm technology occupies only 7,885μm2, which represents an extremely small silicon area.

The test of analog, mixed-signal and RF circuits has been a topic of active research for more than 25 years. Many ideas have been presented at conferences and published in journals. Despite this strong activity, it is still a hot topic that attracts many submissions in major test conferences. Does this mean that all ideas proposed so far are useless or, instead, is the domain in constant evolution facing new challenges that necessitate novel ideas? Panelists both from industry and academia, all experts in the domain, will present their arguments on the reason for longevity of the analog test topic and will give their view on the future of this topic, if any… In particular, the following questions will be discussed in this panel: — Is the topic of analog test still “à la mode”? For academia, industry or both? — What are the changes in the past decade that makes the topic still interesting in 2015? — Are there problems already solved? In which area? — Are there problems that still need to be solved? Which aspects are the more relevant for the future? Which analog devices will pose the hardest problems? — Is academia solving the real problems? Is industry providing the right means to solve their real problems, internally or by collaboration? — What could be done as a Community to speed-up progress on analog testing? — Etc.

This paper introduces a new technique for low-cost phase noise production testing from 1-bit signal acquisition. The technique relies on reconstruction of phase fluctuation from the binary vector captured by a digital ATE channel. A dedicated post-processing algorithm is developed that permits phase noise evaluation from the analysis of the reconstructed time-domain phase fluctuation. The technique is validated through hardware measurements and results demonstrate an excellent agreement with conventional phase noise measurements.

The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.

This paper discusses new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. This redundancy is then used during the testing phase to identify suspect predictions and remove the corresponding devices from the alternate test flow. In this paper, we explore various options for implementing model redundancy, based on the use of different indirect measurement combinations and/or different partitions of the training set. The proposed implementations are evaluated on a real case study for which we have production test data from 10,000 devices.

In the context of mission-critical, safety-critical, and remote-controlled applications, it is required to equip systems with self-adapting capabilities. Adaptation is required in post-manufacturing to correct yield loss and achieve zero defective parts-per-million as well as during normal operation to account for different application scenarios and for varying environmental conditions. A self-adaptive system must be capable of providing the required high performances after manufacturing and throughout its normal operation regardless the application scenario wherein it is deployed and despite the varying environmental conditions. In this paper, we describe a generic post-manufacturing self-adaptation technique for RF circuits as well as concurrent self-adaptation techniques for a safety-critical medical sensor for glaucoma diagnosis and for a NFC system which is very sensitive to the environment in which it operates.

This paper introduces a low-cost technique for phase noise testing of complex RF devices. The technique is based on the acquisition of the signal delivered on the IF output by a standard digital Automated Test Equipment (ATE). A dedicated digital processing algorithm is proposed that permits to achieve phase noise evaluation from the captured binary data. An experimental setup is developed to validate the proposed technique and measurements on actual analog signals demonstrate a very good agreement with conventional phase noise measurements.

IR-drop effects are increasingly relevant in context of both design and test. We introduce the event-driven simulator MIRID that calculates the impact of IR-drop to the circuit timing. MIRID performs the simulation on two abstraction levels: timing effects in the gate-level net-list, current and voltage waveform propagation in the electrical model of the power-distribution network (PDN). Switching events at the logic gates are forwarded to the electrical model, where induced currents and their impact on the neighboring PDN nodes are computed. From this information, values of voltages at the Vdd and ground terminals of logic gates are determined, which in turn are used to calculate accurate switching delays of the gates. MIRID supports a generic interface to electrical models, allowing for a seamless integration of arbitrary models of PDN and gate timing. We report experiments based on a simple PDN model that was introduced previously and incorporates a pre-characterized library. The simulation accuracy is validated by matching the results from MIRID and SPICE.

This work investigates new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. We explore various options for implementing model redundancy, based on the use of different indirect measurement combinations and/or different partitions of the training set.

This paper presents an alternate test implementation based on model redundancy that permits to achieve lower prediction errors than a classical implementation, even if training is performed over a small set of devices. The idea is to build different regression models for each specification during the training phase, and then to verify prediction consistency between the different models during the production testing phase. In case of divergent predictions, the devices are removed from the alternate test tier and directed to a second tier where further testing may apply. The approach is illustrated on a real case study that employs production test data from an RF power amplifier. Results show that, on the contrary to the classical implementation where prediction accuracy degrades when reducing the training set size, the proposed approach permits to preserve prediction accuracy independently of the training set size, while only a very small number of devices are directed to the second tier of the test flow.

In this paper, we investigate an alternate test strategy for RF integrated circuits based on DC measurements. A methodology to select the appropriate DC parameters is presented, that allows precise estimation of the DUT performances while minimizing the number of measurements to be carried out. The method is demonstrated both on simulation test data from a Low-Noise Amplifier (LNA) and production test data from a Power Amplifier (PA). Results indicate that good prediction of the RF performances can be achieved using only a reduced number of DC measurements.

In this paper, an alternative test method for MEMS convective accelerometers is presented. It is first demonstrated that device sensitivity can be determined without the use of physical test stimuli by simple electrical measurements. Using a previously developed behavioral model that allows efficient Monte-Carlo simulations, we have established a good correlation between electrical test parameters and device sensitivity. Proposed test method is finally evaluated for different strategies that privilege yield, fault coverage or test efficiency.

In this paper, we investigate the use of standard digital ATE for the analysis of FM-modulated RF signals. The key idea is to use the 1-bit digitizer of a digital test channel in order to convert the frequency information contained in a FM-modulated signal into a timing information contained in a digital bit stream; a post-processing algorithm based on the concept of zero-crossing detection is then employed to retrieve this information. Coherent under-sampling is exploited to extend the capabilities of test equipment with a limited sampling frequency for the analysis of high-frequency signals. The proposed approach is evaluated on two different case studies related to LTE and GSM communication standards. Both simulation and hardware experiments are presented to demonstrate the viability of the technique.

This paper presents a reconstruction technique based on zero-crossing detection that permits analyzing FM-modulated signals using digital ATE channels. The technique relies on sampling of the analog/RF signal through a 1-bit comparator and the post-processing of the resulting bit stream. The proposed solution is validated through both simulation and hardware experiments.

This paper analyzes the impact of simultaneous switching noise (SSN) on the timing behavior of CMOS digital blocks. The concept of instantaneous transfer function is introduced to interpret noisy signals and perform timing measurements on such signals. It is shown that the average swing during switching is the key parameter to predict the noise impact on the delay of a logic path, whereas the peak of noise is not relevant. The influence of structural parameters such as the block topology is evaluated, and the unpredictable aspect of SSN impact on path delay is highlighted.

Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the variations of power/ground lines at the interface between noncoherent logic blocks in order to warn that a logic error is likely to occur. This information can then be used for any scheme that takes corrective actions.

This paper analyzes the logic errors in digital circuits due to the presence of simultaneous switching noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called 'minimum switch condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called 'signal coherence condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.

In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters " (ANC) requires an extremely simple additional circuitry and interconnect.

In this paper, complex mixed signal circuits such as SiP or SOC including several ADCs and DACs are considered. A new DFT technique is proposed allowing the test of this complete set of embedded ADCs and DACs in a fully digital way such that only a simple low cost tester can be used. Moreover, this technique called "analogue network of converters" (ANC) requires an extremely simple additional circuitry and interconnect

This paper presents an electro-thermal on-line testing procedure applied to a MEMS magnetometer. The basic idea consists in: (i) using electro-thermal excitation to superimpose thermal variations to the normal operating mode; and (ii) processing the sensor output to extract the thermally-induced signal. In this work, we investigate the possibility of using a modulation of the excitation signal to produce a low-frequency thermally-based signal at the output of the Wheatstone bridge. Investigations using high-level simulations are conducted to determine appropriate test stimulus and suitable system architecture.

This paper introduces some practical BIST solutions as a basis for a future self-testable MEMS-based magnetic field sensor. It is demonstrated that slight modifications of the system architecture can be used to allow both on-chip generation of electro-thermal stimuli and preprocessing of the sensor response. The external response analysis and thus the test procedure are then strongly simplified and require only a standard digital automatic test equipment.

The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.

The effect of the parasitic values on the ground bounce voltage and on the delay is investigated. Also the effect of ground bounce on the delay in depth paths is analyzed. A ground bounce attenuation proposal is investigated. This can be done using a circuitry to generate ground bounce before the activation of the main circuit. The impact on the circuit delay is observed.

The development of low-cost go/no-go procedures for MEMS production testing is one of the main issues of MEMS manufacturability. In particular, the generation of low-cost test stimuli is a real challenge. In this paper, we investigate the generation of electrically-induced thermal stimuli to test electro-mechanical structures. Static, transient and harmonic responses are studied and it is demonstrated that they can be used for efficient detection and classification of several faulty devices.

The problem of testing the configurable analog blocks (CABs) of field programmable analog arrays (FPAAs) is addressed in This work. The considered fault model comprises deviations in the nominal values of CAB programmable capacitors, deviations in the programmable gains of CAB input amplifiers and stuck-on/stuck-open faults in CAB switches. The problem of test stimuli generation is solved, in a first approach, by using the oscillation test strategy (OTS), which is associated to a test response analysis external to the device under test. In a second approach, a built-in self-test (BIST) scheme is proposed by associating to the OTS an output response analyzer (ORA) built using the internal FPAA resources. Both approaches are validated using the ispPAC10 FPAA from the Lattice Semiconductor Corporation. In the paper, the approaches are compared in terms of fault coverage, test application time and required external hardware resources for testing. Experimental results show that a good compromise of these aspects can be found by taking the best of each approach.

The use of the oscillation test strategy to test configurable analog blocks of field programmable analog arrays (FPAAs) has been proposed previously, solving the complex problem of test stimuli generation. An improvement to that technique is presented in this paper, using the resources of the FPAA to build an output response analyzer. This new approach offers a full built-in self-test scheme with no area overhead and requiring a low cost automatic test equipment. Experiments show the efficiency of the approach in detecting parametric faults of the tested components.

Gate Oxide Short defects are becoming predominant as technology is scaling down. Boolean and I/sub DDQ/ testing of this defect has been widely studied but there is no paper dedicated to delay testing of this defect. So, this paper studies the delay behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance and the GOS location. Because art accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance and location.

International audience

This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time.

We study the voltage and current behavior of Gate Oxide Short faults due to pinholes in the gate oxide. Our objective is to give a detailed analysis of the behavior of the GOS defect taking into account random parameters such as the GOS resistance, the GOS location and the GOS size. To facilitate an accurate analysis, we use a bi-dimensional array, and, since a complete analysis is desired, we derive characteristics of the GOS as a function of its resistance, location and size. Finally, we validate the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.

This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive scheme is developed to palliate the inaccuracy of a basic ramp generator. As a result, the proposed adaptive ramp generator exhibits very good performances in terms of slope precision and ramp linearity while maintaining a low area overhead.

This paper focuses on the detectability of defects causing the gates of transistors in CMOS integrated circuits to float (open), i.e., on floating gate transistor (FGT) faults. Such faults are known to occur in practice. It is increasingly important to consider their detection to meet high quality requirements for circuits fabricated in deep submicrometer technologies. We focus on the detectability of FGT faults by the standard voltage- and current-based production test strategies that we refer to as static voltage (SV), dynamic voltage (DV), and static current (SC) test strategies. We demonstrate how the behavior of the devices caused by FGT faults depends on two classes of technological and topological parameters: the predictable and unpredictable parameters. We show that an FGT fault can induce abnormal logic values, additional delays, or increased power supply current. We introduce the concept of a detectability interval, i.e., the range of values an unpredictable parameter may assume that one allows for the fault detection using a specific test strategy. We illustrate how the detectability intervals for the SV and DV strategies complement that of the SC strategy. In addition, a new test scheme that results in an increased SC detectability of FGT faults is developed. Finally, we demonstrate the effects of initial trapped charges and the effects of coupling to surrounding metal on the detectability intervals of each of the test strategies.

This paper describes a method to obtain a temperature independent analog BIST. The test procedure is based on the reuse of existing analog circuits, configured either as stimuli generators or as signature analyzers. The paper explains the general problem of temperature deviation present in analog BIST, and shows an approach to overcome this limitation, validated by simulation results.

The objective of this paper is to discuss the possibility of reusing the existing hardware originally present in an analog application to implement test functions for a completely autonomous self-testable solution. In this first approach, a 8/sup th/ order analog linear filter is used as an application example. The required modifications in the circuit are presented with the results in terms of area overhead and fault coverage.

The paper proposes a BIST approach for deriving the main characterization parameters of ADCs from histogram data. An adequate choice of input stimuli and time decomposition scheme is proposed in order to minimize the extra on-chip hardware required to extract these parameters. The idea of time decomposition consists in replacing classical hardware-consuming concurrent calculations by hardware-saving time-spread calculations. The decomposition technique is used both at high level (specific test phases are dedicated to each ADC parameter computation) and low level (sequential steps inside each test phase). Pseudo-algorithms are given to derive offset, gain error and nonlinearities.

This paper studies the Boolean (Static Voltage) and the I/sub ddq/ (Static Current) detection of Floating Gate faults due to large opens on transistor gate connections. We show that existing electrical models describing the behavior of FGT faults fail to allow the prediction of the floating gate potential due to the unpredictable parameters such as the initial changes and the polysilicon-to-bulk capacitance. We propose the twin-transistor structure as a basis for a general analysis of the Boolean and I/sub ddq/ detection of FGT faults. Using this analysis, optimal conditions for detection are defined for Boolean as well as I/sub ddq/ tests.

In this paper, a cost-effective DFT solution for the testing of ring oscillator-based VCOs is presented. The strategy is based on the reconfiguration concept: we propose to modify the circuit so that the VCO operates as a digital structure in test mode. The test can then be performed on a standard digital tester, avoiding the use of costly mixed-signal test equipment. In addition, simulation results show that the use of an adequate digital test strategy permits one to obtain better fault coverage than a classical functional center frequency test.

In this paper, a BIST scheme is proposed that applies to any kind of SI building blocks constituted of an aggregate of identical memory cells. The fundamental idea is to reconfigure the building block into a cascade of memory cells so that the output current is equal in magnitude to the input current. Using a very simple circuitry, an error current can then easily be generated that permits one to detect faults in the block.

The paper describes an approach to optimize the application of the multi-configuration DFT technique for analog circuits. This technique allows to emulate the circuit in a number of new test configurations targeting the maximum fault coverage. The brute force application of the multi-configuration is shown to produce a very significant improvement of the original poor testability. An optimized approach is proposed to apply this DFT technique in a more refined way. The optimization problem consists in choosing among the various permitted test configurations, a set that leads to the best testability/cost trade-off. This set is selected according to ordered requirements: (i) the fundamental requirement of maintaining the maximum fault coverage and (ii) non-fundamental requirements of satisfying some user-defined cost functions such as test time, silicon overhead or performance degradation. Results are given that exhibit very interesting features in terms of either test procedure simplicity or DFT penalty reduction.

In this paper a DFT technique is proposed that provides the full controllability and observability of each memory cell of a switched-current circuit. The technique is proven to be applicable to any kind of SI circuits, very easy to automate and without any impact on the circuit performance. Indeed, the hardware configuration of the circuit is preserved and only the timing configuration is managed to convert the circuit into a fully testable structure in test mode.

A Design-For-Testability (DFT) technique for analog circuits, called the Multi-Configuration technique is presented. This technique exhibits some flexibility features since different solutions are possible for its implementation. Different degrees of granularity are associated to the different solutions, corresponding to a given trade-off between implementation cost and test and/or diagnosis facilities. The multi-configuration technique is illustrated and validated on a 8/sup th/ order band pass filter.

This paper concerns the test of mixed-signal circuits. A novel DFT approach for analog parts constituted of several op-amp-based modules is presented. The idea is to bring the testability resources (controllability and observability) on the frontier of each embedded module by creating transparent paths between external and local I/O's. The key point of this transformation is to permit each analog stage to have a test mode for which it is converted into a follower stage. Adaptative solutions are proposed depending of the availability of on-chip digital resources eventually re-usable to manage analog test. The testability cost is shown to be very low in terms of additional circuitry, number of extra pins, analog response penalty and test management. A case study is presented that demonstrates the applicability of the method.