Demo Data from VLDB 2026 / reviewers in the wild / expert
Russell W. Quong
dblp:49/3435
· DBLP profile ↗
8ranked-venue papers
3as first author
0since 2021 · last 1995
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 5 · 2 first-authorSystems, architecture and hardware · 3 · 1 first-authorTheory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 53% Performance modeling and evaluation · 31% Parallel and multicore computing · 16% | |
| Software engineering, system software, and programming languages
3 papers |
Compilers and program optimization · 65% Software maintenance and evolution · 25% Operating systems · 10% |
Topics — the 6 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems
cache design |
0.0 | 1 | 1994 | Expected I-Cache Miss Rates via the Gap Model · ISCA 1994 |
Performance modeling and evaluation
cache performance modeling |
0.0 | 1 | 1994 | Expected I-Cache Miss Rates via the Gap Model · ISCA 1994 |
Memory systems › cache › CPU cache
instruction cache |
0.0 | 1 | 1994 | Expected I-Cache Miss Rates via the Gap Model · ISCA 1994 |
Compilers and program optimization › compiler toolchain
linking |
0.0 | 1 | 1991 | Linking Programs Incrementally · ACM Trans. Program. Lang. Syst. 1991 |
Performance modeling and evaluation
workload characterization |
0.0 | 1 | 1994 | Expected I-Cache Miss Rates via the Gap Model · ISCA 1994 |
Memory systems › memory management
fragmentation |
0.0 | 1 | 1991 | Eliminating Memory for Fragmentation Within Partitionable SIMD/SPMD Machines · IEEE Trans. Parallel Distributed Syst. 1991 |
Methods — techniques the papers use, named apart from their topics
symbolic trace analysis · 0.0gap model · 0.0LRU stack model · 0.0overflow space allocation · 0.0module allocation · 0.0instrumentation · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1995 | ANTLR: A Predicated- LL(k) Parser GeneratorabstractAbstract Despite the parsing power of LR/LALR algorithms, e.g. YACC, programmers often choose to write recursive‐descent parsers by hand to obtain increased flexibility, better error handling, and ease of debugging. We introduce ANTLR, a public‐domain parser generator that combines the flexibility of hand‐coded parsing with the convenience of a parser generator, which is a component of PCCTS. ANTLR has many features that make it easier to use than other language tools. Most important, ANTLR provides predicates which let the programmer systematically direct the parse via arbitrary expressions using semantic and syntactic context; in practice, the use of predicates eliminates the need to hand‐tweak the ANTLR output, even for difficult parsing problems. ANTLR also integrates the description of lexical and syntactic analysis, accepts LL(k) grammars for k > 1 with extended BNF notation, and can automatically generate abstract syntax trees. ANTLR is widely used, with over 1000 registered industrial and academic users in 37 countries. It has been ported to many popular systems such as the PC, Macintosh, and a variety of UNIX platforms; a commercial C++ front‐end has been developed as a result of one of our industrial collaborations. Terence Parr, Russell W. Quong |
Softw. Pract. Exp. | 2 |
| 1994 | Adding Semantic and Syntactic Predicates To LL(k): pred-LL(k)
Terence Parr, Russell W. Quong |
CC | 2 |
| 1994 | Expected I-Cache Miss Rates via the Gap ModelabstractTo evaluate the performance of a memory system, computer architects must determine the miss rate m of a cache C when running program P. Typically, the measured miss rate depends on the specific address mapping M of P set arbitrarily by the compiler and linker. The author removes the effect of the address-mapping on the miss rate by analyzing a symbolic trace T of basic blocks. By assuming each basic block has an equal probability of ending up anywhere in the address map, he determines the expected miss rate averaged over all possible address mappings. The resulting gap model gives the expected miss rate for instruction caches of varying cache size, line size, and set associativity. The model is simple but robust, and turns out to be the familiar LRU stack model with a statistical viewpoint. The model allows a trace of arbitrary length to he compactly summarized in a few thousand bytes of information. It also predicts how an intervening trace, such as an operating system call or a task switch, will affect the miss rate. Comparisons to measured miss rates from SPEC 92 instruction traces show that the model typically has relative differences of less than 20% for a variety of cache parameters.> Russell W. Quong |
ISCA | 1 |
| 1992 | Fast Average-Case Pattern Matching by Multiplexing Sparse Tables
Russell W. Quong |
Theor. Comput. Sci. | 1 |
| 1991 | Linking Programs IncrementallyabstractLinking is traditionally a batch process that resolves cross-references between object modules and run-time libraries to produce a stand-alone executable image. Because most program changes only involve a small part of the program, we have implemented an incremental linker, named Inclink, that processes only the changed modules. Inclink generates a new executable in time proportional to the size of change; in contrast, a batch linker generates an executable in time proporitonal to the size of the program. To minimize updates to the executable, Inclink allocates extra space for every module. By allocating 24 percent more space in the executable for overflows, Inclink can update a module in place over 97 percent of the time. Measurements show that Inclink is more than an order of magnitude faster than the UNIX [2] batch linker and that 88 percent of all links will take less than 2 s of CPU time on a MicroVAX-2, independent of program size. Russell W. Quong, Mark A. Linton |
ACM Trans. Program. Lang. Syst. | 1 |
| 1991 | Eliminating Memory for Fragmentation Within Partitionable SIMD/SPMD MachinesabstractEfficient data layout is an important aspect of the compilation process. A model for the creation of perfect memory maps for large-scale parallel machines capable of user-controlled partitionable single-instruction-multiple data/single-program-multiple data (SIMD/SPMD) operation is developed. The term perfect implies that no memory fragmentation occurs and ensures that the memory map size is kept to a minimum. A major constraint on solving this problem is based on the single program nature of both the SIMD and SPMD modes of parallelism. It is assumed that all processors within the same submachine used identical addresses to access corresponding data items in each of their local memories. Necessary and sufficient conditions are derived for being able to create perfect memory maps, and results are applied to several partitionable interconnection networks.> Mark A. Nichols, Howard Jay Siegel, Henry G. Dietz, Russell W. Quong, Wayne G. Nation |
IEEE Trans. Parallel Distributed Syst. | 4 |
| 1990 | Minimizing Memory Requirements for Partitionable SIMD/SPMD Machines
Mark A. Nichols, Howard Jay Siegel, Henry G. Dietz, Russell W. Quong, Wayne G. Nation |
ICPP (1) | 4 |
| 1989 | A Macroscopic Profile of Program Compilation and LinkingabstractTo profile the changes made to programs during development and maintenance, the authors have instrumented the 'make' utility that is used to compile and link programs. With minor modifications, they have used 'make' to find out how much time programmers spend waiting for compiling and linking, how many modules are compiled each time a program is linked, and the change in size of the compiled modules. Measurements show that most programs are relinked after only one or two modules are recompiled, and that over 90% of all recompilations yield object code that is less than 100 bytes larger in size. The authors are using these results to guide the design of an incremental programming environment, particularly with respect to an incremental linker.> Mark A. Linton, Russell W. Quong |
IEEE Trans. Software Eng. | 2 |