The first generation CELL processor presented a test challenge in that the chip incorporated multiple processing elements, several multi-gigahertz synchronous and asynchronous clock domains, and many custom design elements. The test objective for the CELL design was to have high test coverage and a small test time. In addition to the objectives mentioned above, the CELL test logic is designed to support a modular design point and support for partial good processing elements. This paper will give an overview of the manufacturing test elements that were designed into the CELL processor.

Latch-to-latch timing rules that ensure the proper operation of synchronous systems are presented and analyzed. The rules state bounds on the amount of propagation delay for the combinational logic between consecutive latch pairs in a digital design. If the bounds are satisfied in a design, then setup and hold times are met throughout the design for each latch on each cycle of machine operation. The rules are quite general in that they apply to systems with multiple skew levels (a feature of most real systems), with multiple latch parameters such as clock to data propagation delays, data to data propagation delays, and setup and hold times, and with multiple clock pulse widths and clock phases. The abstract notion of a clock skew hierarchy is introduced and characterized. The rules are established by a novel and robust method.>

The minimum table size is established for nonrestoring division algorithms that utilize a table lookup technique for quotient digit selection. It is assumed that the dividend and divisor are n-bit fractions, that the algorithm is radix 2q, q ≥ 2, and that the algorithm uses the table on an iteration in which any remainder in the range 0 to 1/2 – 1/2n+1can occur as, for example, in the first iteration. In addition, it is shown how to construct tables that apply to both positive and negative remainders where negative remainders are represented in 2's complement mode.