This paper presents a practical approach to parasitic extraction enabling accurate timing and crosstalk analyses throughout the design cycle. New error indexes, are first proposed for evaluating the accuracy of flat parasitic extraction. The requirements for extraction in hierarchical design flows are then discussed. The methodology reported aims at reducing the gap between the parasitic values estimated with incomplete design and the results of post-layout extraction. The objective is to obtain consistent interconnect models in top-down and bottom-up design flows. This methodology was integrated into the design flow for the 800 MHz UltraSPARC-III microprocessor. Our experimental results demonstrate the profound impact of the extraction methodology on interconnect modeling as well as subsequent timing and noise analyses.

In today’s design of VLSI high speed circuits, frequency has a major impact on the number of repeaters that needs to be inserted. A microprocessor operating at less than 200Mhz might require several hundred repeaters, while one operating at greater than 500Mhz may require a number in the thousands. The following paper describes an efficient and simple way to automatically determine buffer placement based on maintaining equal transition time for all gate input signals across the net. A maximum allowable transition time is determined (limited by the frequency of the circuit), and correlated with the interconnect Elmore Delay. A Spice RC model having nodes with physical locations (X, Y coordinates) can be obtained by extraction tools providing standard parasitic format (SPF). This can then be used with the results of the algorithm for repeater placement to determine the exact physical location desired for each repeater. 1.

Time-domain simulation of circuits which contain analog functional blocks such as gain stages, filters and analog-digital conversion modules can be concurrently simulated with digital components on an event-driven digital simulator. A technique for modeling such analog circuits using digital behavior models has been developed. The simulation of mixed analog-digital circuits based on this methodology has been implemented on an accelerated digital simulator. An automated gain control circuit is presented as an example.>