New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power savings can be realized if 5 V designs are translated to use the new lower supply voltage standards. This conversion, however, is not achieved easily: a design originally targeted for implementation in a 5 V technology will typically require significant rework to meet timing and throughput requirements at the lower operating voltage. In this paper we describe a high-level synthesis system which assists the designer in performing this task, minimizing the need for manual redesign. Techniques employed in this work include pipelining and a new approach to module selection that minimizes power consumption subject to timing constraints. Using these and other high-level synthesis techniques to target designs to 3.3 V libraries, we show that it is possible to reduce power consumption by as much as 56% as compared to the original 5 V implementation, while meeting specified minimum throughput and maximum latency constraints.

An objective of DSP testing should be to ensure that any errors due to missed faults are infrequent compared to a circuit's intrinsic errors, such as overflow. A method is proposed for quantifying test quality for digital filters by measuring the risk associated with any untested faults. Techniques for finding upper bounds on fault activation rates under worst-case operating conditions are described. These techniques enable test designers to objectively discriminate significant missed faults from near-redundant faults, which are unlikely to be activated in normal operation of the device. This complements fault coverage as a measure of test quality, providing a means of locating high-risk missed faults even in very high coverage test regimes.

Test issues in application-specific digital filter datapaths are investigated. It is found that such designs can contain hundreds of redundant faults, making it difficult to accurately determine fault coverage. Since these redundant faults tend to appear in the same general location as test-resistant faults, the presence of many redundant faults can hide significant untested faults despite high overall test coverage. Classes of redundant faults that arise in digital filter datapaths are described, and we propose a suite of techniques for identifying and eliminating the most common redundancies based on arithmetic optimization. The approach is suitable as a front-end to more accurate fault simulation, or can be used in the design process to eliminate redundant logic. The approach is validated as a tool for developing very high-coverage built-in self-test circuits, showing that 100% fault coverage can be achieved in 24k-gate filters with as little as 1% area overhead. When used as a datapath optimization technique, the average area reduction over 15 designs was 8.9%, compared with moderately optimized designs. As a front-end to fault simulation, the approach yielded a 97.9% average reduction in the number of undetected faults across the 15 designs.

We examine frequency-domain issues in the design and selectionof on-chip test generators for built-in self-test (BIST) of high-performancedigital filters. Test-generator/circuit compatibility isidentified as a significant factor in testing large filters. A fault-injectionexperiment is used to show that when an incompatible testgenerator is used, high fault coverage (over 99%) does not guaranteethat all serious faults will be detected. The frequency-domaincharacteristics of some basic test generation schemes are examined,and guidelines for test generator selection are proposed. Analyticaltechniques for identifying frequency-related testability problemsare discussed, and several test generation schemes are evaluated byfault simulating them against lowpass, bandpass, and highpass filters.A mixed test generation scheme is shown to reduce the numberof untested faults by a factor of two to three over a standard linear-feedbackshift-register (LFSR) based test scheme, at little added cost.

The testability of basic DSP datapath structures using pseudorandom built-in self-test techniques is examined.The addition of variance mismatched signals is identified as a testing problem, and the associated fault detection probabilities are derived in terms of signal probability distributions.A method of calculating these distributions is described, and it is shown how these distributions can be used to predict testing problems that arise from the correlation properties of test sequences generated using linear-feedback shift registers.Finally, it is shown empirically that variance matching using associativity transformations can reduce the number of untested faults by a factor of eight over variance mismatched designs.

Pseudorandom built-in self-test (BIST) is an attractive means of testing DSP datapath structures as long as the delay and area overhead can be kept low. One obstacle to low-overhead BIST is random-pattern test-resistant datapath structures. We examine the causes of this resistance in some typical DSP datapaths, and introduce variance mismatch as an analytical tool for identifying these test problems. By understanding the mechanisms behind random-pattern test resistance, it is possible to make design decisions that are compatible with pseudorandom BIST, resulting in reduced test length and higher fault coverage. Variance matching theory is applied to the design of two large FIR filters, resulting in an 88% reduction in the number of missed faults for a fixed test length, and two orders-of-magnitude reduction in test length for a specific fault coverage target.

Testability problems that arise in the design of fixed-coefficient finite impulse response (FIR) filters are examined. A class of redundant faults that naturally derive from the structure and behavior of these filters are examined, and design-for-test (DFT) techniques based on scaling theory are used to eliminate the redundancies. Eliminating these redundancies makes it possible for built-in self-test (BIST) approaches to reach 100% coverage, and automatic test-pattern generation (ATPG) based approaches can benefit by more than an order of magnitude reduction in test generation time. A case study provides a demonstration of the approach.

New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power servings can be realized if 5 V designs are translated to use the new lower supply voltage standards. This conversion, however is not achieved easily: a design originally targeted for implementation in a 5 V technology will typically require significant re-work to meet timing and throughput requirements at the lower operating voltage. We describe a high-level synthesis system which assists the designer in performing this task, minimizing the need for manual re-design. Techniques employed in this work include pipelining and a new approach to module selection which minimizes power consumption subject to timing constraints. Using these and other high-level synthesis techniques to target designs to 3.3 V libraries, we show that it is possible to reduce power consumption by as much as 56% as compared to the original 5 V implementation, while meeting specified minimum throughput and maximum latency constraints.>