Demo Data from VLDB 2026 / reviewers in the wild / expert
Hendrik Post
dblp:50/1951
· DBLP profile ↗
8ranked-venue papers
6as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 7 · 6 first-authorSystems, architecture and hardware · 1Theory of computation · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Embedded and real-time systems · 33% | |
| Software engineering, system software, and programming languages
2 papers |
Program verification · 57% Program analysis · 38% Requirements engineering and software design · 6% |
Topics — the 9 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems
automotive electronics |
0.2 | 1 | 2014 | Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges · DAC 2014 |
Electronic design automation
hardware verification and test |
0.2 | 1 | 2014 | Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges · DAC 2014 |
Electronic design automation › system-level design
virtual prototyping |
0.2 | 1 | 2014 | Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges · DAC 2014 |
Program analysis › static analysis
abstract interpretation |
0.1 | 1 | 2008 | Reducing False Positives by Combining Abstract Interpretation and Bounded Model Checking · ASE 2008 |
Program verification › model checking
bounded model checking |
0.1 | 1 | 2008 | Reducing False Positives by Combining Abstract Interpretation and Bounded Model Checking · ASE 2008 |
Program analysis › static analysis › bug detection
false positive reduction |
0.1 | 1 | 2008 | Reducing False Positives by Combining Abstract Interpretation and Bounded Model Checking · ASE 2008 |
Program verification
model checking |
0.1 | 1 | 2008 | Configuration Lifting: Verification meets Software Configuration · ASE 2008 |
Program verification
product-line verification |
0.1 | 1 | 2008 | Configuration Lifting: Verification meets Software Configuration · ASE 2008 |
Requirements engineering and software design
software product lines |
0.0 | 1 | 2008 | Configuration Lifting: Verification meets Software Configuration · ASE 2008 |
Methods — techniques the papers use, named apart from their topics
virtual prototyping · 0.2static analysis · 0.1model checking · 0.1deduction-based verification · 0.1bounded model checking · 0.1abstract interpretation · 0.1SAT solving · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research ChallengesabstractIntelligent automotive electronics significantly improved driving safety in the last decades. With the increasing complexity of automotive systems, dependability of the electronic components themselves and of their interaction must be assured to avoid any risk to driving safety due to unexpected failures caused by internal or external faults. Jan-Hendrik Oetjens, Nico Bannow, Markus Becker 0001, Oliver Bringmann 0001, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le 0001, Andreas Mauderer, Wolfgang Müller 0003, Daniel Mueller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter 0003, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl |
DAC | 18 |
| 2013 | Advanced features for industry-level logging and tracing of C-based designs
Wei Hong 0005, Jyoti Joshi, Alexander Viehl, Nico Bannow, Angela Kramer, Hendrik Post, Oliver Bringmann 0001, Wolfgang Rosenstiel |
FDL | 6 |
| 2009 | Proving Functional Equivalence of Two AES Implementations Using Bounded Model CheckingabstractBounded model checking-as well as symbolic equivalence checking-are highly successful techniques in the hardware domain. Recently, bit-vector bounded model checkers like CBMC have been developed that are able to check properties of (mostly low-level) software written in C. However, using these tools to check equivalence of software implementations has rarely been pursued. In this case study we tackle the problem of proving the functional equivalence of two implementations of the AES crypto-algorithm using automatic bounded model checking techniques. Cryptographic algorithms heavily rely on bit-level operations, which makes them particularly suitable for bit-precise tools like CBMC. Other software verification tools based on abstraction refinement or static analysis seem to be less appropriate for such software. We could semi-automatically prove equivalence of the first three rounds of the AES encryption routines. Moreover, by conducting a manually assisted inductive proof, we could show equivalence of the full AES encryption process. Hendrik Post, Carsten Sinz |
ICST | 1 |
| 2009 | Linking Functional Requirements and Software VerificationabstractSynchronization between component requirements and implementation centric tests remains a challenge that is usually addressed by requirements reviews with testers and traceability policies. The claim of this work is that linking requirements, their scenario-based formalizations, and software verification provides a promising extension to this approach. Formalized scenarios, for example in the form of low-level assume/assert statements in C, are easier to trace to requirements than traditional test sets. For a verification engineer, they offer an opportunity to better participate in requirements changes. Changes in requirements can be more easily propagated because adapting formalized scenarios is often easier than deriving and updating a large set of test cases. The proposed idea is evaluated in a case study encompassing over 50 functional requirements of an automotive software developed at Robert Bosch GmbH. Results indicate that requirement formalization together with formal verification leads to the discovery of implementation problems missed in a traditional testing process. Hendrik Post, Carsten Sinz, Florian Merz 0001, Thomas Gorges, Thomas Kropf |
RE | 1 |
| 2009 | Towards automatic software model checking of thousands of Linux modules - a case study with AvinuxabstractAbstract Modular software model checking of large real‐world systems is known to require extensive manual effort in environment modelling and preparing source code for model checking. Avinux is a tool chain that facilitates the automatic analysis of Linux and especially of Linux device drivers. The tool chain is implemented as a plugin for the Eclipse IDE, using the source code bounded model checker CBMC as its backend. Avinux supports a verification process for Linux that is built upon specification annotations with SLICx (an extension of the SLIC language), automatic data environment creation, source code transformation and simplification, and the invocation of the verification backend. In this paper technical details of the verification process are presented: Using Avinux on thousands of drivers from various Linux versions led to the discovery of six new errors. In these experiments, Avinux also reduced the immense overhead of manual code preprocessing that other projects incurred. Copyright © 2008 John Wiley & Sons, Ltd. Hendrik Post, Carsten Sinz, Wolfgang Küchlin |
Softw. Test. Verification Reliab. | 1 |
| 2008 | Configuration Lifting: Verification meets Software ConfigurationabstractConfigurable software is ubiquitous, and the term software product line (SPL) has been coined for it lately. It remains a challenge, however, how such software can be verified over all variants. Enumerating all variants and analyzing them individually is inefficient, as knowledge cannot be shared between analysis runs. Instead of enumeration we present a new technique called lifting that converts all variants into a meta-program, and thus facilitates the configuration-aware application of verification techniques like static analysis, model checking and deduction-based approaches. As a side-effect, lifting provides a technique for checking software feature models, which describe software variants, for consistency. We demonstrate the feasibility of our approach by checking configuration dependent hazards for the highly configurable Linux kernel which possesses several thousand of configurable features. Using our techniques, two novel bugs in the kernel configuration system were found. Hendrik Post, Carsten Sinz |
ASE | 1 |
| 2008 | Reducing False Positives by Combining Abstract Interpretation and Bounded Model CheckingabstractFully automatic source code analysis tools based on abstract interpretation have become an integral part of the embedded software development process in many companies. And although these tools are of great help in identifying residual errors, they still possess a major drawback: analyzing industrial code comes at the cost of many spurious errors that must be investigated manually. The need for efficient development cycles prohibits extensive manual reviews, however. To overcome this problem, the combination of different software verification techniques has been suggested in the literature. Following this direction, we present a novel approach combining abstract interpretation and source code bounded model checking, where the model checker is used to reduce the number of false error reports. We apply our methodology to source code from the automotive industry written in C, and show that the number of spurious errors emitted by an abstract interpretation product can be reduced considerably. Hendrik Post, Carsten Sinz, Alexander Kaiser 0001, Thomas Gorges |
ASE | 1 |
| 2007 | Integrated Static Analysis for Linux Device Driver Verification
Hendrik Post, Wolfgang Küchlin |
IFM | 1 |