The number of independent input pins used to control the electrodes in digital microfluidic “biochips” is an important cost-driver in the emerging market place, especially for disposable PCB devices that are being developed for clinical and point-of-care diagnostics. However, most prior work on pin-constrained biochip design considers droplet routing and the assignment of pins to electrodes as independent problems. In this paper, we propose optimization methods to solve the droplet routing and pin-constrained design problems concurrently. First, we formulate the co-optimization problem involving droplet routing and pin-mapping. Next, we present an integer linear programming-based optimization method to solve the droplet-routing and the pin-mapping design problems concurrently. The proposed co-optimization method minimizes the number of control pins. We also present an efficient heuristic approach to tackle the co-optimization problem. These methods overcome a major drawback of a recently proposed method, which leads to infeasible solutions involving conflicts in the mapping of pins to electrodes in different droplet-routing stages. The effectiveness of the proposed co-optimization method is demonstrated for two commercial biochips and an experimental university chip for multiplexed in-vitro diagnostics.

Recent advances in digital microfluidics have enabled droplet-based biochip devices for DNA sequencing, immunoassays, clinical chemistry, and protein crystallization. Since cross-contamination between droplets of different biomolecules can lead to erroneous outcomes for bioassays, the avoidance of cross-contamination during droplet routing is a key design challenge for biochips. We propose a droplet-routing method that avoids cross-contamination in the optimization of droplet flow paths. The proposed approach targets disjoint droplet routes and synchronizes wash-droplet routing with functional droplet routing, in order to reduce the duration of droplet routing while avoiding the cross-contamination between different droplet routes. In order to avoid cross-contamination between successive routing steps, an optimization technique is used to minimize the number of wash operations that must be used between successive routing steps. Two real-life biochemical applications are used to evaluate the proposed droplet-routing methods.

The implementation of bioassays in pin-constrained digital microfluidic biochips may involve pin-actuation conflicts if the concurrently-implemented fluidic operations are not carefully synchronized. We propose a two-phase optimization method to identify and synchronize the fluidic operations that can be executed in parallel. The goal is to implement these fluidic operations without pin-actuation conflict, and minimize the duration of implementing the outcome sequence after synchronization. We also extend the synchronization method with the addition of a small number of control pins, in order to further minimize the completion time while avoiding pin-actuation conflicts. The effectiveness of the proposed synchronization method is demonstrated for a representative 3-plex assay performed on a commercial pin-constrained biochip and for multiplexed in-vitro diagnostics performed on an experimental pin-constrained biochip.

The number of independent input pins used to control the electrodes in digital microfluidic "biochips" is an important cost-driver in the emerging market place, especially for disposable PCB devices that are being developed for clinical and point-of-care diagnostics. However, most prior work on pin-constrained biochip design considers droplet routing and the assignment of pins to electrodes as independent problems. We propose aninteger linear programming (ILP)-based optimization method to solve the droplet-routing and the pin-mapping design problems concurrently. The proposed co-optimization method optimizes routing pathways, generates a single pin-assignment, and attempts to minimize the number of control pins. It also overcomes a major limitation of recent work on this problem---the method described in prior work can lead to infeasible designs due to the need to change the mapping of pins to electrodes dynamically during bioassay execution. The effectiveness of the proposed co-optimization method is demonstrated for a commercial biochip that is used to perform n-plex immunoassays, as well as an experimental chip for multiplexed in-vitro diagnostics.

Recent advances in digital microfluidics have enabled lab-on-a-chip devices for DNA sequencing, immunoassays, clinical chemistry, and protein crystallization. Basic operations such as droplet dispensing, mixing, dilution, localized heating, and incubation can be carried out using a 2-D array of electrodes and nanoliter volumes of liquid. The number of independent input pins used to control the electrodes in such microfluidic “biochips” is an important cost-driver, especially for disposable printed circuit board devices that are being developed for clinical and point-of-care diagnostics. However, most prior work on biochip design-automation has assumed independent control of the electrodes using a large number of input pins. We present a broadcast-addressing-based design technique for pin-constrained multifunctional biochips. The proposed method provides high throughput for bioassays and it reduces the number of control pins by identifying and connecting control pins with “compatible” actuation sequences. We also describe two scheduling methods to map fluidic operations on the pin-constrained design, in order to minimize the completion time while avoiding pin-actuation conflicts. The proposed methods are evaluated using multifunctional chips designed to execute a set of multiplexed bioassays, the polymerase chain reaction, and a protein dilution assay.

Digital micro fluidic biochips with non-regular arrays are of interest for clinical diagnostic applications in a cost-sensitive market segment. Previous techniques for biochip testing are limited to regular micro fluidic arrays. We present an automatic test pattern generation (ATPG) method for non-regular digital micro fluidic chips. The ATPG method can generate test patterns to detect catastrophic defects in non-regular arrays where the full reconfigurability of the digital micro fluidic platform is not utilized. It automates test-stimulus design and test-resource selection, in order to minimize the test application time. We also present an integer linear programming model for the compaction of test patterns, while maintaining the desired fault coverage. We utilize a fabricated biochip with non-regular micro fluidic arrays to evaluate the proposed ATPG method.

Digital microfluidic biochips are being utilized in many areas of biochemistry and biomedical sciences. Since cross-contamination between droplets of different biomolecules can lead to erroneous outcomes for bioassays, it is essential to avoid cross-contamination during droplet routing. We propose a wash-operation synchronization method to manipulate wash droplets to clean the residue that is left behind by sample and reagent droplets. We also synchronize wash-droplet routing with sample/reagent droplet-routing steps by controlling the arrival order of droplets at cross-contamination sites. The proposed method minimizes droplet-routing time without cross-contamination, and it is especially effective for tight chip-area constraints. A real-life application is used for evaluation.

On-line testing offers a promising method for detecting defects, fluidic abnormalities, and bioassay malfunctions in microfluidic biochips. To reduce product cost for disposable biochips, testing steps and functional fluidic operations must be implemented on pin-constrained designs. However, previous testing methods for pin-constrained designs do not optimize test schedules to reduce the number of control pins and test/assay completion time. We propose a pin-count-aware online testing method for pin-constrained designs to support the execution of both fault testing and the target bioassay protocol. The proposed method interleaves fault testing with the target bioassay protocol for online testing. It is aimed at significantly reducing the completion time for testing and for the bioassay, while keeping the number of control pins small. Two practical applications, namely a multiplexed bioassay and an interpolation-based mixing protocol, are used to evaluate the effectiveness of the proposed method.

Recent advances in digital microfluidics have led to tremendous interest in miniaturized lab-on-chip devices for biochemical analysis. Synthesis tools have also emerged for the automated design of lab-on-chip from the specifications of laboratory protocols. However, none of these tools consider control flow or address the problem of recovering from fluidic errors that can occur during on-chip bioassay execution. We present a synthesis method that incorporates control paths and an error-recovery mechanism in the design of a digital microfluidic lab-on-chip. Based on error-propagation estimates, we determine the best locations for fluidic checkpoints during biochip synthesis. A microcontroller coordinates the implementation of the control-flow-based bioassay by intercepting the synthesis results that are mapped to the software programs. Real-life bioassay applications are used as case studies to evaluate the proposed design method. For a representative protein assay, compared to a baseline chip design, the biochip with a control path can reduce the completion time by 30% when errors occur during the implementation of the bioassay.

Recent advances in droplet-based digital microfluidics have enabled biochip devices for DNA sequencing, immunoassays, clinical chemistry, and protein crystallization. Since cross-contamination between droplets of different biomolecules can lead to erroneous outcomes for bioassays, the avoidance of cross-contamination during droplet routing is a key design challenge for biochips. We propose a droplet-routing method that avoids cross-contamination in the optimization of droplet flow paths. The proposed approach targets disjoint droplet routes and minimizes the number of cells used for droplet routing. We also minimize the number of wash operations that must be used between successive routing steps that share unit cells in the microfluidic array. Two real-life biochemical applications are used to evaluate the proposed droplet-routing methods.

Dependability is an important system attribute for microfluidic lab-on-chip devices. On-line testing offers a promising method for detecting defects, fluidic abnormalities, and bioassay malfunctions during chip operation. However, previous techniques for reading test outcomes and analyzing pulse sequences are cumbersome, sensitive to the calibration of capacitive sensors, and error-prone. We present a built-in self-test (BIST) method for on-line testing of digital microfluidic lab-on-chip. This method utilizes microfluidic compactors based on droplet-based AND gates, which are implemented using digital microfluidics. Dynamic reconfiguration of these compactors ensures low area overhead and it allows BIST to be interleaved with bioassays in functional mode.

Dependability is an important system attribute for microfluidic lab-on-chip. Structural test and functional test are needed to detect defects and malfunctions, respectively. Previously proposed techniques for reading test outcomes and for pulse-sequence analysis are cumbersome and error-prone. We present a built-in self-test (BIST) method for digital microfluidic lab-on-chip. This method utilizes digital microfluidic logic gates to implement the BIST architecture; AND, OR and NOT gates are used to compress test-outcome droplets into one droplet signature. This approach obviates the need for capacitive sensing test-outcome circuits for analysis. An efficient diagnosis method based on a microfluidic encoder is also proposed to locate a single defective electrode in a microfluidic array. Finally, reconfiguration is used during test and diagnosis to enable BIST with low area overhead.

We present a new scan-based built-in self-test (BIST) technique, which is based on weighted scan-enable signals and a reconfigurable scan-forest architecture. A testability measure is proposed to guide test pattern generation and produce patterns with few care bits. This approach can effectively reduce the amount of test data that needs to be stored on-chip. The proposed BIST method relies on the pseudorandom and deterministic phases. The scan-forest architecture is configured as a single scan tree for deterministic test vector application in the second phase. It is found that a linear feedback shift register, with size equal to the maximum number of the care bits in the deterministic patterns for the random-resistant faults, is sufficient to encode deterministic vectors for the benchmark circuits. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method for single stuck-at faults. In addition, experimental results show that the patterns applied to the circuit under test provide more n-detection than those applied by a traditional scan-chain architecture with a single test session.

Test generation and fault simulation of path delay faults are very time-consuming. A new fault simulation method of fully enhanced scan designed circuits is proposed for path delay faults based on single stuck-at tests without circuit transformation. The proposed method identifies robustly and non-robustly testable paths first, for which a selected path circuit (SPC) is constructed. The SPC circuit contains no internal fanouts. Fault simulation of non-robustly testable paths is reduced to 3-valued logic simulation of the SPC circuit. Fault simulation is completed on the SPC circuit by only tracing the active part of SPC circuit. An effective fault dropping technique is also adopted based on the selective tracing scheme. The proposed fault simulation scheme is extended to that of robustly testable path delay faults. Experimental results confirm that the proposed fault simulator is exact. It is shown according to experimental results that the proposed fault simulator gets exact fault simulation results in very short time. Sufficient experimental results are presented to compare with previous methods on CPU time and accuracy.

The paper presents a new scan-based BIST technique, which is based on weighted scan enable signals and a scan forest architecture. A new testability measure is proposed to guide test pattern generation and produce patterns with fewer specified bits. This approach can effectively reduce the amount test data that needs to be stored on-chip. The proposed BIST method relies on a pseudorandom phase and a deterministic phase. The scan forest architecture is configured as a single scan tree for deterministic test vector application in the second phase. It is found that an LFSR with size equal to the maximum number of the specified bits in the deterministic patterns for the random-resistant faults is sufficient to encode deterministic vectors for the benchmark circuits. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method