Voltage reference circuits are crucial components within analog and mixed-signal integrated circuits, serving fundamental roles in maintaining stability and accuracy. Through examining bipolar circuits from both circuit and layout design viewpoints, we have introduced several new techniques to tackle challenges that were overlooked in previous studies. These techniques include 1) a Wilson current mirror structure, 2) a base current compensation resistor, 3) temperature-compensating resistors, 4) fuse trimming, 5) improved lateral PNP transistor design, and 6) a common-centroid layout for NPN transistors. The proposed circuit architecture is realized using a 1.5μm, 32V bipolar process. Measurement outcomes demonstrate that it achieves a temperature coefficient as low as 4.9ppm/∘C. Post-irradiation with a total dose of 500 krad (Si), the voltage reference exhibited a minimal variation of 0.10%, fulfilling the criteria for single-event latch-up resistance with a Linear Energy Transfer (LET) threshold exceeding 80.5 MeV⋅cm2/mg.

This paper presents a high-precision bandgap voltage reference (BGR) using a low-cost current trimming network. The high-order curvature compensation is implemented by injecting a current with concave temperature curve characteristics into the bandgap core circuit. Meanwhile, a current-based trimming circuit is proposed to obtain a precise reference voltage while reducing the circuitry complexity and area consumption. Compared with traditional resistor-based trimming networks, the proposed trimming scheme does not require large-area resistors and complex digital logic circuits. Compared with prior current-based trimming scheme, the proposed one does not require extra current mirrors. The proposed BGR was designed in a 180nm BCD process and post-layout simulation results show that the temperature coefficient (TC) is lower than 2.3 ppm/°C within a wide temperature range of -40℃ to 125℃. Additionally, the power supply rejection ratio (PSRR) of -69dB at 100Hz is achieved. The active area of the proposed BGR is 383 µm × 259 µm, where the area of the proposed trimming circuit only occupies 16%.

Dynamic voltage and frequency scaling (DVFS) is commonly used for the balance of performance and power of mobile processors. Conventional DVFS regulators take the processor cores with the same power and performance weight showing their inability in the regulation of heterogeneous processors. This paper proposes a core-aware frequency-power evaluation scheme that utilizes a multilayer perceptron (MLP) to assess the efficacy of DVFS regulation actions. Additionally, a ResNet-based DVFS regulator, trained with the assistance of the MLP, is developed for heterogeneous multi-core processors. Evaluated on Xiaomi 13 Pro powered by a Qualcomm Snapdragon 8 Gen 2, the proposed DVFS approach achieves an up to ×1.47 improvement in FPS Performance Per Watt (FPPW) compared with the Qualcomm's default DVFS governor in video recording scenario.

The fast-growing development in wearable electronic devices leads to high demand for small-volume, lightweight, and high-efficiency DC-DC power converters, particularly switched capacitor (SC) DC-DC converters. In this paper, we propose a synthesis framework of step-down SC DC-DC power converters to obtain an optimum converter topology under the design constraints of the conversion ratio and a minimum number of capacitors. The proposed rule-based clustering reduction techniques have reduced the search space and sped up the conversion ratio analysis. In the case study of 8:1 converter synthesis, the run-time for conversion ratio analysis is reduced by 1.26$\boldsymbol{\times}$$\boldsymbol{10^6}$. The proposed efficiency optimization method has improved the peak efficiencies of the cascaded 2:1 converter and Fibonacci converter by 4.7% and 12.8%. The proposed framework has identified new topologies and variants of conventional topologies. The variant of cascaded 2:1 converter shows an improvement of 8.2% on peak efficiency.

Reinforcement learning (RL) based dynamic voltage and frequency scaling (DVFS) is an effective approach to balance performance and power consumption for video rendering applications. To approximate the “God’s eye view” regulation, the CPU-GPU should be fine-grained regulated and the SoC have to be fully observed by a RL-based DVFS governor. Fine-grained regulation with traditional value-based RL governor suffers action space explosion and it is impossible to have a fully observable SoC. To address these two issues, a governor based on deep recurrent deterministic gradient (DRDPG) governor is proposed. The governor is based on Deterministic Policy Gradient (DDPG) algorithm with embedded recurrent neural network (RNN). The DDPG algorithm guarantees fine-grained power regulation without action space explosion and the RNN-FC network topology mitigates the partial observability issue. Evaluated on the Nvidia Jetson NX platform, the proposed DRDPG governor achieves over 19% better regulation efficiency compared with Linux default governors and shows superior regulation efficiency to other RL-based state-of-the-arts. Implemented in a 55-nm CMOS process, the proposed governor draws merely 2.16-mA from a 1.2-V supply at 1-MHz clock occupying a silicon area of 0.075mm$^2$.

This paper presents the analysis and behavioral modeling of two high-order DAC linearity enhancement techniques and constructs a third-order noise-shaping (NS) SAR ADC with full-bit high-order mismatch-shaped capacitor DAC(CDAC) to verify the performance. The CDAC is divided into an MSB segment and two LSB segments, where a third-order VMS and a second-order MES are utilized to deal with the capacitance mismatch respectively. With the enhancement of the behavioral model, optimizations focused on the mismatch transfer function (MTF) and segment length of MSB and LSB are made. The simulation results of obtained system achieve 113.25dB SNDR and 18.52 ENOB when 1% CDAC mismatch is introduced.