The global demographic shift toward an aging population presents a critical socio-economic challenge, necessitating "aging in place" solutions that balance autonomy with safety. Although the Internet of Medical Things (IoMT) offers a theoretical foundation for remote monitoring, current implementations often fail to meet real-world requirements due to high costs, intrusive sensing modalities, and a lack of contextual reasoning. This article outlines the architectural requirements of the next-generation platform for digital health support. We argue that the future of monitoring the elderly lies within the framework of Agentic Artificial Intelligence (AI), a system that not only records events but also reasons about them, detects and adapts to anomalies, and communicates with caregivers through natural language. As a result, the next generation of digital wellness platforms must bridge the gap between technical data and human understanding, providing high-precision detection, human-readable, and context-aware recommendations. This shifts systems from simple data loggers to proactive decision-supporting tools.

Ensuring both electrical performance and effective thermal management in large-scale battery packs is a critical challenge for next-generation electric mobility and energy storage systems. Current modeling approaches often rely on rigid configurations or computationally expensive CFD simulations, limiting their use in early design stages. This work introduces a modular, compositional framework that enables the dynamic construction of battery packs of arbitrary size, where each cell is modeled individually with coupled electrical and thermal dynamics. The framework integrates a configurable liquid cooling system supporting multiple layouts and coolant types, allowing rapid evaluation of thermal management strategies under diverse operating conditions. By combining scalability, flexibility, and high computational efficiency, the proposed approach accelerates design iterations, reduces prototyping costs, and supports the development of safer and more reliable battery systems for real-world applications.

Metaverse environments combined with large language models (LLMs) enable guided interaction through LLM-powered avatars that function as embodied conversational agents. In our study, we examined how scholars interact with an LLM-powered avatar modeled after a real professor during a virtual reality (VR) tour of a research lab. As little is known about how metaverse characteristics shape the user experience (UX) mechanisms that drive acceptance of such technologies, we conducted a 2 (avatar realism: abstract vs. hyperrealistic) × 2 (immersion: desktop vs. headset-based VR) within-subjects study (N= 30), where academic participants engaged in a virtual lab tour guided by the professor avatar. We conducted path analyses on three conceptual models and, based on the results, proposed the Virtual Lab Acceptance Model (VLAM), which features an experiential path (where perceived immersion increases empathy towards the avatar and task enjoyment) and a rational path (where perceived realism increases avatar credibility and task confidence). Flow states amplify these pathways by strengthening task experiences. Task enjoyment is the strongest predictor of behavioral intention. These findings inform HCI research on metaverse characteristics to drive technology acceptance through UX mechanisms, yielding design implications for developing LLM-powered avatars for virtual labs.

With the advent of Industrial 4.0 and the push toward Industry 5.0, the data generated by the industries have become surprisingly large. This abundance of data significantly boosts machine and deep learning models for Predictive Maintenance (PdM). The PdM plays a vital role in extending the lifespan of industrial equipment and machines while also helping to reduce the risk of unscheduled downtime. Given its multidisciplinary nature, the field of PdM has been approached from many different angles: this comprehensive survey aims at providing an up-to-date overview focused on all the learning-based industrial PdM strategies, discussing weaknesses and strengths. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing a systematic and complete review of the literature. In particular, firstly, we explore the main learning models used for PdM, mainly Convolutional Neural Networks (ConvNets), Autoencoders (AEs), Generative Adversarial Networks (GANs), and Transformers, also giving an overview of the newest models such as diffusion models and foundation models. Then, we discuss the main learning paradigms applied to PdM, i.e., supervised, unsupervised, ensemble, transfer, federated, and reinforcement learning. Furthermore, this work discusses the pipeline of the data-driven PdM and its benefits, practical applications, datasets, and benchmarks. In addition, the evaluation metrics for each PdM stage and the state-of-the-art hardware devices used are discussed. Finally, the challenges and future work are presented.

Moving beyond the automation-driven paradigm of Industry 4.0, Industry 5.0 emphasizes human-centric industrial systems where human creativity and instincts complement precise and advanced machines. With this new paradigm, there is a growing need for resource-efficient and user-preferred manufac-turing solutions that integrate humans into industrial processes. Unfortunately, methodologies for incorporating human elements into industrial processes remain underdeveloped. In this work, we present the first pipeline for the creation of a human-centered Digital Twin (DT), leveraging Unreal Engine's MetaHuman technology to track worker alertness in real-time. Our findings demonstrate the potential of integrating Artificial Intelligence (AI) and human-centered design within Industry 5.0 to enhance both worker safety and industrial efficiency.

Smart factories are complex environments equipped with both production machinery and computing devices that collect, share, and analyze data. For this reason, the modeling of today's factories can no longer rely on traditional methods, and computer engineering tools, such as SysML, must be employed. At the same time, the current SysML v1. * standard does not provide the rigorousness required to model the complexity and the criticalities of a smart factory. Recently, SysML v2 has been proposed and is about to be released as the new version of the standard. Its release candidate version shows the new version aims at providing a more rigorous and complete modeling language, able to fulfill the requirements of the smart factory domain. In this paper, we explore the capabilities of the new SysML v2 standard by building a rigorous modeling strategy, able to capture the aspects of a smart factory related to the production process, the computation and the communication. We apply the proposed strategy to model a fully-fledged smart factory, and we rely on models to automatically configure the different pieces of equipment and software components in the factory.

Batteries are a central component of many complex systems, including mobile devices, sensors, electric vehicles, etc. Keeping the battery working in normal conditions avoids dangerous hazards for the user or the system itself and helps extend the device’s life. The battery temperature is one of the most delicate aspects of these devices since some dangerous scenarios, like thermal runaway, could occur due to variable conditions. This paper uses a battery model of an electric vehicle from the automotive area as a case study to simulate the thermal response to normal usage. Then, thermal fault scenarios are modeled within equivalent circuital device descriptions and analyzed regarding state-of-charge, temperature, and voltage output. The findings presented offer a valuable starting point for improving the design phase of the batteries in multiple fields by testing fault scenarios already during simulation.

This paper presents an architecture for automated fault recovery in special-purpose machinery using standard IEC 61131-3 PLC control software. Building upon the MAPE-K paradigm (Monitor, Analyze, Plan, Execute with Knowledge), the proposed three-level architecture integrates runtime control via a previously presented modularization concept called Control Primitives, high-level reasoning using Regionalized Resource Process Dependence Graphs (RRPDGs), and an intermediate Resource Agent that bridges field-level execution and recovery planning. The architecture supports fully automated dynamic recovery and seamless resumption of productive operations while maintaining real-time reliability. Experimental evaluation demonstrates the scalability and low resource demands of the planning system across simulated scenarios and validates the concept on a lab-sized real-world demonstrator. The architecture and interfaces build a modular foundation for future research and industrial applications.

The complexity of current manufacturing systems is growing, increasing the complexity of testing and validating control software. Manufacturing software must be extensively tested to minimize errors that may lead to production stops or machine breakdowns. However, testing on real manufacturing systems is often impractical or limited to small portions of the real systems. This paper presents Frost, an open-source platform supporting early manufacturing software validation and testing. Frost is built on top of the Lingua Franca framework, which ensures deterministic execution, enhancing the reliability of software prototyping and testing. The proposed platform implements a set of reactors and classes designed to model the different parts of a manufacturing system, such as sensors, machines, control software, and communication infrastructure. The effectiveness and capabilities of the Frost platform are validated by comparing the overhead introduced and by implementing a digital twin of a real manufacturing system.

Defect detection is the task of identifying defects in production samples. Usually, defect detection classifiers are trained on ground-truth data formed by normal samples (negative data) and samples with defects (positive data), where the latter are consistently fewer than normal samples. State-of-the-art data augmentation procedures add synthetic defect data by superimposing artifacts to normal samples to mitigate problems related to unbalanced training data. These techniques often produce out-of-distribution images, resulting in systems that learn what is not a normal sample but cannot accurately identify what a defect looks like. In this work, we introduce DIAG, a training-free Diffusion-based In-distribution Anomaly Generation pipeline for data augmentation. Unlike conventional image generation techniques, we implement a human-in-the-loop pipeline, where domain experts provide multimodal guidance to the model through text descriptions and region localization of the possible anomalies. This strategic shift enhances the interpretability of results and fosters a more robust human feedback loop, facilitating iterative improvements of the generated outputs. Remarkably, our approach operates in a zero-shot manner, avoiding time-consuming fine-tuning procedures while achieving superior performance. We demonstrate the efficacy and versatility of DIAG with respect to state-of-the-art data augmentation approaches on the challenging KSDD2 dataset, with an improvement in AP of approximately 18 % when positive samples are available and 28 % when they are missing. The source code is available at https://github.com/intelligolabs/DIAG.

This paper introduces a framework to integrate Financial Operations (FinOps) practices in Kubernetes, addressing the challenge of managing cloud services' costs across multicloud environments. The framework automates the collection of service providers' costs by deploying Prometheus exporters and scrapers, then standardizes cost data according to the FinOps Cost and Usage Specification (FOCUS) through Large Language Models (LLMs). It enables automatic data analysis, implemented by a metrics aggregator, to compute insightful cost and quality of service optimizations. We present the experimental results on three standard cloud service providers, achieving up to 91% accuracy in automatic data standardization. The results corroborate that the framework helps simplify cloud cost management and promote FinOps principles.

Split Computing (SC), where a Deep Neural Network (DNN) is intelligently split with a part of it deployed on an edge device and the rest on a remote server is emerging as a promising approach. It allows the power of DNNs to be leveraged for latency-sensitive applications that do not allow the entire DNN to be deployed remotely, while not having sufficient computation bandwidth available locally. In many such embedded systems scenarios, such as those in the automotive domain, computational resource constraints also necessitate Multi-Task Learning (MTL), where the same DNN is used for multiple inference tasks instead of having dedicated DNNs for each task, which would need more computing bandwidth. However, how to partition such a multi-tasking DNN to be deployed within a SC framework has not been sufficiently studied. This paper studies this problem, and MTL-Split, our novel proposed architecture, shows encouraging results on both synthetic and real-world data. The source code is available at https://github.com/intelligolabs/MTL-Split.

Detecting complex anomalies on massive amounts of data is a crucial task in Industry 4.0, best addressed by deep learning. However, available solutions are computationally demanding, requiring cloud architectures prone to latency and bandwidth issues. This work presents VARADE, a novel solution implementing a light autoregressive framework based on variational inference, which is best suited for real-time execution on the edge. The proposed approach was validated on a robotic arm, part of a pilot production line, and compared with several state-of-the-art algorithms, obtaining the best trade-off between anomaly detection accuracy, power consumption and inference frequency on two different edge platforms.

With the rise of Machine Learning (ML) and Artificial Intelligence (AI), the semiconductor industry is undergoing a revolution in how it approaches manufacturing. The SMART-IC project (DATE'24 MPP category: initial stage) works in this direction, by proposing an AI-enabled framework to support the smart monitoring and optimization of the semiconductor manufacturing process. An AI-powered engine examines sensor data recording physical parameters during production (like gas flow, temperature, voltage, etc.) as well as test data, with different goals: (1) the identification of anomalies in the production chain, either offline from collected data-traces or online from a continuous stream of sensed data; (2) the forecasting of new data of the future production; and (3) the automatic generation of synthetic traces, to strengthen the data-based algorithms. All such tasks provide valuable information to an advanced Manufacturing Execution System (MES), which reacts by optimizing the production process and management of the equipment maintenance policies. SMART-IC is a 300k€ academic project funded by the Italian Ministry of University and supported by STMicroelectronics and Technoprobe with industrial expertise and real-world applications. This paper shares the view of SMART-IC on the future of semiconductor manufacturing, the preliminary efforts, and the future results that will be reached by the end of the project, in 2025.

The DeFacto project, supported by the European Commission via a Marie Skłodowska-Curie Global Individual Fellowship, tackles the complexity arising from the transformation of industrial manufacturing systems into intricate cyber-physical systems. This evolution offers unprecedented opportunities but also poses intellectual and engineering challenges. DeFacto aims to advance the design automation of cyber-physical production systems by developing innovative modeling paradigms, scalable algorithms, software architectures, and tools. In the DeFacto approach, production systems are managed through service-oriented manufacturing software architectures. System-level models capture the features and the requirements of production systems, representing both production and computational processes as services provided by the infrastructure. Methodologies for system analysis and optimization rely on compositional abstractions of system behaviors grounded in assume-guarantee contracts. This paper outlines key research endeavors, findings, and lessons learned from the DeFacto project.

Industrial control systems need to be highly reliable and precise at all times to ensure operational efficiency and prevent costly downtime. Early fault detection is crucial and is partially realized by runtime monitoring components. A correct-by-construction approach based on contract specifications allows early intervention in case of potential faults. In this paper, we suggest to combine the time-sensitive behavioral contracts with a multi-domain system model specifically designed for fault injection to improve the model as well as the contract specification at design time. This allows for early detection of potential faults and a more reliable system specification based on the analyzed behavior. We successfully realized a co-simulation environment comprising a fault-injection tool and contract-based monitors. We discussed the proposed approach using the example of a DC motor highlighting the benefits and potential enhancements of this systematic methodology.

Smart manufacturing systems often use data to optimize production processes. Artificial intelligence algorithms can be used to tune the parameters of production recipes to achieve the desired results. Indeed, such algorithms will require to be trained by using data collected while executing manufacturing operations. However, the required sets of data are rarely available to most production companies. This work-in-progress paper introduces the Print+Mill dataset: a collection of data related to additive and subtractive manufac-turing operations. The data are collected during the execution of various production recipes, utilizing different materials and process parameters. For each recipe, the dataset includes data on the materials and parameters used, sensor readings from the machinery, such as power consumption and temperature, and information on the quality of the resulting product. The data are collected in a complex research facility; in the future, we plan to extend the dataset by considering other manufacturing operations, materials, and types of field data.

In the past decade, Deep Neural Networks (DNNs) achieved state-of-the-art performance in a broad range of problems, spanning from object classification and action recognition to smart building and healthcare. The flexibility that makes DNNs such a pervasive technology comes at a price: the computational requirements preclude their deployment on most of the resource-constrained edge devices available today to solve real-time and real-world tasks. This paper introduces a novel approach to address this challenge by combining the concept of predefined sparsity with Split Computing (SC) and Early Exit (EE). In particular, SC aims at splitting a DNN with a part of it deployed on an edge device and the rest on a remote server. Instead, EE allows the system to stop using the remote server and rely solely on the edge device’s computation if the answer is already good enough. Specifically, how to apply such a predefined sparsity to a SC and EE paradigm has never been studied. This paper studies this problem and shows how predefined sparsity significantly reduces the computational, storage, and energy burdens during the training and inference phases, regardless of the hardware platform. This makes it a valuable approach for enhancing the performance of SC and EE applications. Experimental results showcase reductions exceeding 4× in storage and computational complexity without compromising performance. The source code is available at https://github.com/intelligolabs/sparsity_sc_ee.

Creating a virtual model of a real system brings several advantages before its effective fabrication, especially in the design phases. Simulating a system is helpful for determining whether and what improvements need to be brought to the prototype or for testing changes given by the presence of faults. In this context exploiting the features of a gaming engine created mainly for video game purposes for simulating physical prototypes could reveal new research perspectives. Advanced rendering capabilities, physical simulation, and accuracy in describing different materials obtainable make this environment very attractive even beyond the gaming world. Another key feature that can be obtained with these simulators is the combination of accurately modeled physical properties and graphical rendering of physical behaviors. Together, they generate a visualization that is physically accurate and graphically realistic. For this reason, this article examines the development of behavioral models inside the Unreal Engine gaming environment, mainly based on the C++ language. The models created will be used for design analysis, performance monitoring, and improvement research. The model chosen as a case study is a digital twin of a DC Motor simulated in normal operating conditions and in the presence of faults.

Under the pressure of the Industry 4.0 revolution, and now with the European Chips Act, smart systems are becoming omnipresent in all industrial sectors, e.g., automotive and aerospace. Such systems contain digital and analog components belonging to several physical domains, e.g., electrical and mechanical. To ensure robustness, the whole system must be validated as early as possible in the development cycle, by taking into account all such domains, as recommended by the ISO 26262 standard in the case, e.g., of automotive systems. Unfortunately, validation techniques, including fault injection and simulation are not as advanced on the analog side as the digital counterpart: i) they are not fully standardized ii) they are highly domain-dependent, and iii) they are performed separately from the digital flow. This article proposes to improve the design of smart systems by generating faulty scenarios through analog fault injection across several physical domains. By exploiting these faulty scenarios, it is possible to improve the robustness of the analog part and, at the same time, to improve the quality of the digital part that controls the system functionality. A multi-domain case study containing a microcontroller and a three-axis accelerometer is presented to demonstrate the validity of the proposed approach in many industrial contexts.

The design of manufacturing systems requires exploring diverse component configurations for one that best satisfies the requirements of the target system. At the same time, manufacturing systems evolve continuously, increasing their complexity and that of the production line in which they are installed. Model-based System Engineering (MBSE) methodologies and modeling languages like System Modeling Language (SysML) are used to assist system engineers during the entire design process. Yet, MBSE methodologies mainly rely on manually composed models for requirements verification, incurring enormous cost and effort especially in larger, more complex systems. This paper proposes a methodology exploiting the knowledge enclosed in a SysML model to automate the execution of a set of analyses defined over the represented manufacturing system. The proposed approach relies on Lingua Franca (LF) to simulate the specified analysis and analyze the results. Moreover, the methodology supports chains of analyses to represent dependent requirements and tradeoffs imposed upon a manufacturing system. The proposed methodology has been evaluated on a manufacturing system demonstrator. Results show the proposed methodology's applicability and scalability on diverse configurations of the manufacturing system.

The continuous evolution of Industry 4.0 demands advanced solutions for optimizing production processes, reducing energy consumption, and enhancing the capabilities of both human operators and production devices in smart factories. As factory automation software becomes increasingly complex, ensuring its robustness through extensive testing is critical. However, testing on actual production systems is often impractical due to the critical nature of the software.This paper explores the use of digital twins to simulate factory environments, enabling thorough validation of automation software. We propose leveraging Lingua Franca and the Functional Mock-up Interface (FMI) standard to create comprehensive digital twins. Lingua Franca ensures deterministic execution in simulations, while FMI facilitates the integration of diverse simulators for accurate modeling of heterogeneous systems. We introduce an interfacing method to integrate FMI components within Lingua Franca and present a strategy for modeling software-machinery interactions using the OPC Unified Architecture (OPC UA) protocol. The methodology is applied to develop a digital twin of a logistics subsystem in a manufacturing system, demonstrating the effectiveness of the simulation environment through various scenarios.

The safety of aircraft heavily depends on the in-tegrity of the Landing Gear System (LGS). However, gathering real-world fault data to support effective Prognostic and Health Management (PHM) practices presents significant challenges. This work proposes a novel methodology for generating synthetic fault data using a multi-physics Simscape model of a landing gear deployment/retraction mechanism. The model incorporates specialized fault blocks designed to replicate various hydraulic failure modes, aiming to broaden the pool of fault data covering the most common failures. This approach promises to enhance maintenance strategies and facilitate the development of hybrid Model-Based and Data-Driven solutions. Ultimately, the results of this study will be used to understand the physics within the landing gear better and gather the necessary data to create an effective Digital Twin for predictive maintenance.

Smart systems contain digital and analog components of several physical domains, e.g., electrical and mechanical During the design phase, the fault injection, which checks the system functionality following the guidelines of ISO standard 26262, enhances the system’s robustness. Unfortunately, fault injection and simulation on the analog side are i) not fully standardized compared to their digital counterparts, ii) highly domain-dependent, and iii) performed separately from the digital. This article proposes to improve the design of smart systems by generating faulty scenarios through analog fault injection across several physical domains. By exploiting these faulty scenarios it is possible to improve the robustness of the analog part and simultaneously improve the quality of the digital part that controls the system functionality.

This study addresses the challenge of deploying robotic software with Quality of Service (QoS) constraints in Edge-Cloud computing clusters. The paper introduces HEFT4K, an event-driven scheduling method tailored for Kubernetes-managed systems based on the Heterogeneous Early Finish Time (HEFT) algorithm. This algorithm reduces software execution time (makespan) and facilitates re-mapping in case of node failures, involving only essential containers to maintain uninterrupted robot functionality. Experimental results, conducted on a real-world robot and synthetic benchmarks, show a 75% speedup in makespan compared to the standard Kubernetes scheduler, enhancing the efficiency of QoS-focused scheduling for robotic applications in distributed systems.

There is an increasing interest in exploiting human pose estimation (HPE) software in human-machine interaction systems. Nevertheless, adopting such a computer vision application in real industrial scenarios is challenging. To overcome occlusion limitations, it requires multiple cameras, which in turn require multiple, distributed, and synchronized HPE software nodes running on resource-constrained edge devices. We address this challenge by presenting a real-time distributed 3D HPE platform, which consists of a set of 3D HPE software nodes on edge devices (i.e., one per camera) to redundantly extrapolate the human pose from different points of view. A centralized aggregator collects the pose information through a shared communication network and merges them, in real time, through a pipeline of filtering, clustering and association algorithms. It addresses network communication issues (e.g., delay and bandwidth variability) through a two-levels synchronization, and supports both single and multi-person pose estimation. We present the evaluation results with a real case of study (i.e., HPE for human-machine interaction in an intelligent manufacturing line), in which the platform accuracy and scalability are compared with state-of-the-art approaches and with a marker-based infra-red motion capture system.

In this paper, we present an example of complete integration of eXtended Reality technologies within a demonstration laboratory showcasing Industry 4.0/5.0 compliant machinery in realistic scenarios of use. We describe the design choices and the implementation of the augmented and virtual reality applications developed and potentially usable to support different real-world tasks, featuring advanced gesture-based interaction modes. We also describe the optimized communication architecture used to synchronize data between the cyber-physical factory environment with all its components, its industrial digital twin, and the augmented and virtual replica of the factory. Example tasks supported with the tools in public demonstrations allow users wearing Microsoft HoloLens 2 or Meta Quest 2 headsets to monitor the status of the prototype production line and operate on it, locally or remotely. An example video showing the applications is available in the supplementary material.

Over the last decade, the industrial world has been involved in a massive revolution guided by the adoption of digital technologies. In this context, complex systems like cyber-physical systems play a fundamental role since they were designed and realized by composing heterogeneous components. The combined simulation of the behavioral models of these components allows to reproduce the nominal behavior of the real system. Similarly, a smart system is a device that integrates heterogeneous components but in a miniaturized form factor. The development of smart or cyber-physical systems, in combination with faulty behaviors modeled for the different physical domains composing the system, enables to support advanced functional safety assessment at the system level. A methodology to create and inject multi-domain fault models in the analog side of these systems has been proposed by exploiting the physical analogy between the electrical and mechanical domains to infer a new mechanical fault taxonomy. Thus, standard electrical fault models are injected into the electrical part, while the derived mechanical fault models are injected directly into the mechanical part. The entire flow has been applied to two case studies: a direct current motor connected with a gear train, and a three-axis accelerometer.

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions.

Human-centered robotic applications are becoming pervasive in the context of robotics and smart manufacturing, and such a pervasiveness is even more expected with the shift to Industry 5.0. The always increasing level of autonomy of modern robotic platforms requires the integration of software applications from different domains to implement artificial intelligence, cognition, and human-robot/robot-robot interaction. Developing and (re)configuring such a multi-domain software to meet functional constraints is a challenging task. Even more challenging is customizing the software to satisfy non-functional requirements such as real-time, reliability, and energy efficiency. In this context, the concept of Edge-Cloud continuum is gaining consensus as a solution to address functional and non-functional constraints in a seamless way. Containerization and orchestration are becoming a standard practice, as they allow for better information flow among different network levels as well as increased modularity in the use of multi-domain software components. Nevertheless, the adoption of such a practice along the design flow, from simulation to the deployment of complex robotic applications by addressing the de facto development standards (e.g., ROS - Robotic Operating System) is still an open problem. We present a design methodology based on Docker and Kubernetes that enables containerization and orchestration of ROS-based robotic SW applications for heterogeneous and hierarchical HW architectures. The methodology aims at (i) integrating and verifying multi-domain components since early in the design flow, (ii) mapping software tasks to containers to minimize the performance and memory footprint overhead, (iii) clustering containers to efficiently distribute load across the edge-cloud architecture by minimizing resource utilization, and (iv) enabling multi-domain verification of functional and non-functional constraints before deployment. The article presents the results obtained with a real case of study, in which the design methodology has been applied to program the mission of a Robotnik RB-Kairos mobile robot in an industrial agile production chain. We have obtained reduced load on the robot’s HW with minimal performance and network overhead, thanks to the optimized distributed system.

This article introduces the regionalized resource process dependence graphs (RRPDGs): a manufacturing processes representation inspired by the regionalized value state dependence graphs traditionally used in software compilers. An RRPDG is an ordered sequence of nodes, each characterized by stereotyped input and output parameters, encapsulating a transformation of the process state (e.g., a manufacturing operation). RRPDG allow defining complex transformations by composing a set of nodes (i.e., regions), hiding the internal details. Then, RRPDGs are used to automatically reasoning over dynamic reconfiguration and process optimization: an instance of the A-star search algorithm is used to search for possible transformations while pursuing an optimization function. The rules defined in this article over RRPDG models enforce the transformations' correctness. We use RRPDGs to model a real production system while the transformation rules are applied to optimize the system's processes. The proposed representation reduced the search complexity in each experiment, allowing to reach an optimal solution also in the case for which classical approaches were unable to complete before reaching the timeout. In all the experiments, the cost of the solution produced by using the regionalized representation is minor than the the solution produced by using the classical representation.

Containerization and orchestration have become two key requirements in software development best practices. Containerization allows for better resource utilization, platform-independent development, and secure deployment of software. Orchestration automates the deployment, networking, scaling, and availability of containerized workloads and services. While containerization is increasingly being adopted in the robotic community, the use of task orchestration platforms (e.g., Kubernetes) is still an open challenge. The biggest limitation is due to the fact that state-of-the-art orchestrators do not support real-time containers, while advanced robotic software often consists of a mix of heterogeneous tasks (i.e., ROS nodes) with different levels of temporal constraints (i.e., mixed-criticality systems). This work addresses this challenge by presenting RT-Kube, a platform that extends the de-facto reference standard for container orchestration, Kubernetes, to schedule tasks with mixed-criticality requirements. It implements monitoring of tasks and detects missed deadlines for those with real-time constraints. It selects low-priority tasks to be migrated at runtime to different units of the computing cluster to free resources and recover from temporal violations. We present quantitative experimental results on the software implementing the mission of a Robotnik RB-Kairos mobile robot to demonstrate the effectiveness of the proposed approach. The source code is publicly available on GitHub.

In the context of smart buildings and smart cities, the design of low-cost and privacy-aware solutions for recognizing the presence of humans and their activities is becoming of great interest. Existing solutions exploiting wearables and video-based systems have several drawbacks, such as high cost, low usability, poor portability, and privacy-related issues. Consequently, more ubiquitous and accessible solutions, such as WiFi sensing, became the focus of attention. However, at the current state-of-the-art, WiFi sensing is subject to low accuracy and poor generalization, primarily affected by environmental factors, such as humidity and temperature variations, and furniture position changes. Such is-sues are partially solved at the cost of complex data preprocessing pipelines. In this paper, we present a highly accurate, resource-efficient deep learning-based occupancy detection solution, which is resilient to variations in humidity and temperature. The approach is tested on an extensive benchmark, where people are free to move and the furniture layout does change. In addition, based on a consolidated algorithm of explainable AI, we quantify the importance of the WiFi signal w.r.t. humidity and temperature for the proposed approach. Notably, humidity and temperature can indeed be predicted based on WiFi signals; this promotes the expressivity of the WiFi signal and at the same time the need for a non-linear model to properly deal with it.

Many recent pattern recognition applications rely on complex distributed architectures in which sensing and computational nodes interact together through a communication network. Deep neural networks (DNNs) play an important role in this scenario, furnishing powerful decision mechanisms, at the price of a high computational effort. Consequently, powerful state-of-the-art DNNs are frequently split over various computational nodes, e.g., a first part stays on an embedded device and the rest on a server. Deciding where to split a DNN is a challenge in itself, making the design of deep learning applications even more complicated. Therefore, we propose Split-Et-Impera, a novel and practical framework that i) determines the set of the best-split points of a neural network based on deep network interpretability principles without performing a tedious try-and-test approach, ii) performs a communication-aware simulation for the rapid evaluation of different neural network rearrangements, and iii) suggests the best match between the quality of service requirements of the application and the performance in terms of accuracy and latency time.

BDDs are representations of a Boolean expression in the form of a directed acyclic graph. BDDs are widely used in several fields, particularly in model checking and hardware verification. There are several implementations for BDD manipulation, where each package differs depending on the application. This paper presents HermesBDD: a novel multi-core and multi-platform binary decision diagram package focused on high performance and usability. HermesBDD supports a static and dynamic memory management mechanism, the possibility to exploit lock-free hash tables, and a simple parallel implementation of the IF-THEN-ELSE procedure based on a higher-level wrapper for threads and futures. HermesBDD is completely written in C++ with no need to rely on external libraries and is developed according to software engineering principles for reliability and easy maintenance over time. We provide experimental results on the n-Queens problem, the de-facto SAT solver benchmark for BDDs, demonstrating a significant speedup of 18.73× over our non-parallel baselines, and a remarkable performance boost w.r.t. other state-of-the-art BDDs packages.

In this paper, we present the project “VIR2EM: VIrtualization and Remotization for Resilient and Efficient Manufacturing” by providing details on its research themes and its scientific and technological output. The project, centered on virtualization and remotization in the industrial sector, was promoted by Regione Veneto in Italy, and it has seen the participation and collaboration of 3 universities, 1 public research entity, and 10 companies composed of end users of digital solutions and high knowledge-intensive service providers. The project aims to develop and use tools for the virtualization of processes, systems, resources, and remoting of operations in order to: (1) maximize the efficiency of manufacturing systems under normal operating conditions; (2) maintain operations in case of emergency situations; (3) facilitate the restart of operations downstream of emergency situations by ensuring flexibility and predictive capability. Each theoretical proposal has been validated in distinct industrial facilities by constructing ten different prototypes.

Industry 4.0 involves the integration of digital technologies, such as IoT, Big Data, and AI, into manufacturing and industrial processes to increase efficiency and productivity. As these technologies become more interconnected and interdependent, Industry 4.0 systems become more complex, which brings the difficulty of identifying and stopping anomalies that may cause disturbances in the manufacturing process. This paper aims to propose a diffusion-based model for real-time anomaly prediction in Industry 4.0 processes. Using a neuro-symbolic approach, we integrate industrial ontologies in the model, thereby adding formal knowledge on smart manufacturing. Finally, we propose a simple yet effective way of distilling diffusion models through Random Fourier Features for deployment on an embedded system for direct integration into the manufacturing process. To the best of our knowledge, this approach has never been explored before.

With functional safety being increasingly important in the development of mixed-signal products for automotive applications, EDA solutions have appeared striving to help designers in the setup and execution of fault injection campaigns. Despite the ongoing work to standardize the definition of defect models and coverage calculation methods in the IEEE P2427 draft standard, there is a lack of a unified and portable method to define defect templates that can be used to inject in a systematic way defects in an analog circuit. Each of the existing EDA tool sets for fault injection proposes its own proprietary method to specify how defects should be defined and injected. The proposed paper describes a Verilog-A-based approach to coding defect templates, which through compliance with the Verilog-A standard, warrants portability across compatible simulators. The approach has been validated on the circuits from the Analogue Benchmark Circuits made available by the IEEE P2427 working group.

The early detection of anomalous behaviors from a production line is a fundamental aspect of Industry 4.0, facilitated by the collection of massive amounts of data enabled by the Industrial Internet of Things. Nonetheless, the design and validation of anomaly detection algorithms, mostly based on sophisticated Machine Learning models, heavily rely on the availability of annotated datasets of realistic anomalies, which is very difficult to obtain in a real production line. To address this problem, we introduce the Robotic Arm Dataset (RoAD), specifically designed to support the development and validation of Multivariate Time Series Anomaly Detection (MTSAD) algorithms. We collect and annotate a large number of data and metadata to characterize the motion and energy consumption of a collaborative robotic arm in a full-fledged production line and annotate a comprehensive set of healthy as well as realistic anomalies scenarios. To prove the significance of RoAD and encourage future developments, we benchmark several state-of-the-art anomaly detection algorithms on our newly introduced dataset, and we freely release it to the scientific community.

Constructing a holistic digital twin of a system composed of multiple physical domains is crucial for various tasks. In particular, when the simulation is extended with faults, it becomes a very important resource to achieve robust functional safety analysis. This article proposes a new methodology to build non-electrical fault models for the thermal domain. Such thermal faults are defined through an electrical circuit representing the thermal behavior of the system, known as the Cauer network, based on the physical analogies between the two domains. Including this thermal representation in a multi-domain system allows to simulate the interconnections between different physical domains, thus achieving a more realistic system behavior and evaluating the mutual impact of different domains (e.g., mechanical, electrical and thermal). The entire methodology is applied to a complex case of study implemented by using Verilog-AMS as a proof of concept.

This paper presents a software architecture extending the classical automation pyramid to control and reconfigure flexible, service-oriented manufacturing systems. At the Planning level, the architecture requires a Manufacturing Execution System (MES) consistent with the International Society of Automation (ISA) standard. Then, the Supervisory level is automated by introducing a novel component, called Automation Manager. The new component interacts upward with the MES, and downward with a set of servers providing access to the manufacturing machines. The communication with machines relies on the OPC Unified Architecture (OPC UA) standard protocol, which allows exposing production tasks as “services”. The proposed software architecture has been prototyped to control a real production line, originally controlled by a commercial MES, unable to fully exploit the flexibility provided by the case study manufacturing system. Meanwhile, the proposed architecture is fully exploiting the production line's flexibility.

Manufacturing systems require a careful scheduling of the resource usage to maximize the production efficiency. In a completely automated environment, the transport system should be orchestrated to work smoothly with the other resources. While the impact of job characteristics, such as fixed or variable processing times of the tasks composing the jobs, or task dependencies, has been extensively studied, the role of the transport system has received less attention.In this paper we consider a conveyor belt as a mean of transportation among a set of production machines. In this scenario, there is no input or output buffer at the machines, and the transport times depend on the availability of the machines. We propose a heuristic based on randomization, called SCHED-T, which is able to find a near optimal joint schedule for job processing and transfer in few seconds. We test our solution on known benchmarks, along with real-world instances, showing that our scheduler is able to predict accurately the overall processing time of a production line.

There are several languages for modeling a Cyber-Physical System (CPS). One of them is Verilog-AMS, which allows representing a system belonging to the electrical and mechanical physical domains in a single model through different disciplines. A framework for the automatic fault injection in the electrical and mechanical domains is proposed in this context. In particular, starting from a mechanical system, it is possible to represent it as an electrical circuit by exploiting the physical analogies. In the electrical domain, fault modeling and injection techniques are more advanced than in other physical domains. Extending the analogies to fault models makes it possible to apply the electrical fault models in the equivalent circuit to the mechanical system. These yields mechanical-level faulty behaviors, which can be injected into the mechanical domain, resulting in mechanical (physical) faults, depending on the component. It is finally shown an example of execution of this flow through a model of an electric motor, in which mechanical faults are injected. Simultaneously, the equivalent electrical faults are injected into the equivalent electrical circuit.

This work makes a substantial step in the field of split computing, i.e., how to split a deep neural network to host its early part on an embedded device and the rest on a server. So far, potential split locations have been identified exploiting uniquely architectural aspects, i.e., based on the layer sizes. Under this paradigm, the efficacy of the split in terms of accuracy can be evaluated only after having performed the split and retrained the entire pipeline, making an exhaustive evaluation of all the plausible splitting points prohibitive in terms of time. Here we show that not only the architecture of the layers does matter, but the importance of the neurons contained therein too. A neuron is important if its gradient with respect to the correct class decision is high. It follows that a split should be applied right after a layer with a high density of important neurons, in order to preserve the information flowing until then. Upon this idea, we propose Interpretable Split (I-SPLIT): a procedure that identifies the most suitable splitting points by providing a reliable prediction on how well this split will perform in terms of classification accuracy, beforehand of its effective implementation. As a further major contribution of I-SPLIT, we show that the best choice for the splitting point on a multiclass categorization problem depends also on which specific classes the network has to deal with. Exhaustive experiments have been carried out on two networks, VGG16 and ResNet-50, and three datasets, Tiny-Imagenet-200, notMNIST, and Chest X-Ray Pneumonia. The source code is available at https://github.com/vips4/I-Split.

Products and materials traceability is essential in modern manufacturing, where the production must meet certain standards that range from Quality Control (QC) to the quality of the used materials. In this environment, blockchain applications allow certifying data provenience and subsequent modification, offering trust and security along the entire supply chain. Nonetheless, the design and the development of such applications are usually performed manually and, thus, subject to errors.In this paper, we propose a methodology allowing to automatically generate smart contracts starting from a SysML model. This approach allows easing the integration of blockchain applications in a production system: by abstracting the implementations with models, it is possible to generate smart contracts for different blockchains, connecting to multiple production environments.We applied the proposed methodology on a real manufacturing system, assessing the quality of a case-study production.

Containerization promises to strengthen platform-independent development, better resource utilization, and secure deployment of software. As these benefits come with negligible overhead in CPU and memory utilization, containerization is increasingly being adopted in mobile robotic applications. An open challenge is supporting software tasks that have mixed-criticality requirements. Even more challenging is the combination of real-time containers with orchestration, which is an emerging paradigm to automate the deployment, networking, scaling, and availability of containerized workloads and services. This paper addresses this challenge by presenting a framework that extends the de-facto reference standard for container orchestration, Kubernetes, to schedule tasks with mixed-criticality requirements. Quantitative experimental results on the software implementing the mission of a Robotnik RB-Kairos mobile robot demonstrate the effectiveness of the proposed approach. The source code is publicly available on GitHub.

In this article, a predictive fault grouping based on the collection of faulty AC matrices at fault-free operating points is presented as a means to approximate the final distribution of faults in equivalence classes using a minimal computational effort. The method is computationally cheap because it avoids performing DC or transient simulations with faults injected and limits itself only to AC simulations with faults activated. The technique provides an approximation, since it does not characterize faults at the corresponding faulty operating point but instead looks at how they would modify the fault-free operating point once injected.The approximate grouping achieves an excellent correlation to the final classification based on the comparison of faulty transient wave-forms. It is not meant as a substitute for the traditional fault injection simulations but as a support to decision making. It allows prioritizing faults to characterize the possible failure modes with a minimum number of fault injections, pushing out fault injections which are estimated to marginally increase the learning.

Manufacturing lines are evolving into complex cyber-physical production systems. However, their growth in complexity is not matched by the development of structured modeling and design methodologies. In particular, approaches exploiting both models typical of the manufacturing domain and models used by computer engineers are still missing. In this work, we outline a design flow contemplating the reuse of already existing manufacturing lines' models, while designing novel advanced production systems. To enable such a flow, we propose a methodology extracting System Modeling Language (SysML) structural diagrams from AutomationML descriptions. Then, we propose to design the system functionalities on top of the produced diagrams. The paper shows the application of the methodology to a concrete manufacturing line, the structure of which was originally modeled using AutomationML. To exemplify the advantages of the methodology, we exploit the models being generated to automatically extract a digital twin for the production system transportation line. The resulting digital twin is compliant with a well-known plant simulation tool.

There are plentiful successors of SPICE language for describing transistor-level designs. For most of them, the semantic matches those of SPICE, and only the syntax is changed. Others instead provide more default models or analysis tools. Consequently, a commercial tool is usually required for simulating, analyzing, and especially manipulating these languages. This article proposes a framework that relies on the shared semantic for reading, writing, or manipulating transistor-level designs. The ultimate goal of the framework is: reading an input design written in a specific syntax and then allowing to write the same design in another syntax. First, the input description is parsed by a language-specific front-end which turns it into an in-memory abstract syntax tree that follows the common semantic. Then, the in-memory description can be subject to different user-defined manipulations built on top of a series of API or visitor/listener classes. Finally, the description goes through the desired back-end, transforming the in-memory description into the target transistor-level language. As a use-case for the proposed framework, we chose the process of analog fault injection. This activity requires adding, removing, or replacing nodes, components, or even entire sub-circuits. Therefore, the framework is completely written in C++, and its APIs are also interfaced with python. The entire framework is open-source and available on GitHub.

The Industry 4.0 trend speeds up the adoption of a variety of technologies. In modern manufacturing, system data are collected both from the field through sensors and by exploiting complex simulations. Data analysis techniques became crucial to build and maintain any efficient production line, while autonomous systems and robots are the main focus of researchers and practitioners. This pervasive use of artificial intelligence derived technologies pushed humans to the border of production systems. Industry 5.0 aims at bringing the attention back to humans in production lines while magnifying their interactions with intelligent systems. This new trend will impact the design of future manufacturing infrastructures, increasing their complexity. Engineers will need modeling and developing tools able to capture this complexity. In this paper, we analyze the modeling languages and tools being used, identifying their strengths and weaknesses. Then, we propose some possible directions to provide engineers with the expressive power needed to tackle the challenges posed by Industry 5.0.

Programming modern Robots' missions and behavior has become a very challenging task. The always increasing level of autonomy of such platforms requires the integration of multi-domain software applications to implement artificial intelligence, cognition, and human-robot/robot-robot interaction applications. In addition, to satisfy both functional and nonfunctional requirements such as reliability and energy efficiency, robotic SW applications have to be properly developed to take advantage of heterogeneous (Edge-Fog-Cloud) architectures. In this context, containerization and orchestration are becoming a standard practice as they allow for better information flow among different network levels as well as increased modularity in the use of software components. Nevertheless, the adoption of such a practice along the design flow, from simulation to the deployment of complex robotic applications by addressing the de-facto development standards (i.e., robotic operating system - ROS - compliancy for robotic applications) is still an open problem. We present a design methodology based on Docker and Kubernetes that enables containerization and orchestration of ROS-based robotic SW applications for heterogeneous and hierarchical HW architectures. The design methodology allows for (i) integration and verification of multi-domain components since early in the design flow, (ii) task-to-container mapping techniques to guarantee minimum overhead in terms of performance and memory footprint, and (iii) multi-domain verification of functional and non-functional constraints before deployment. We present the results obtained in a real case of study, in which the design methodology has been applied to program the mission of a Robotnik RB-Kairos mobile robot in an industrial agile production chain. The source code of the mobile robot is publicly available on GitHub.

This paper presents DOHMO, an embedded computer vision system where multiple sensors, including intelligent cameras, are connected to actuators that regulate illumination and doors. The system aims at assisting elderly and impaired people in co-housing scenarios, in accordance with privacy design principles. The paper provides details of two core elements of the system: The first one is the BOX-IO controller, a fully scalable and customizable hardware and software IoT ecosystem that can collect, control, and monitor data, operational flows and business scenarios, whether indoor or outdoor. The second one is the embedded 3DEverywhere intelligent camera, a device composed of an embedded system that receives input data provided by a 3D/2D camera, analyzes it, and returns the metadata of this analysis. We illustrate how they can be connected and how simple decision mechanisms can be implemented in such a framework. In particular, illumination can be triggered on and off by the detected presence of people, overcoming the limitations of typical sensors, while doors can be opened or closed based on person trajectories in an intelligent manner. To substantiate the proposed system, numerous experiments are performed in a lab and a co-housina scenario.

This article presents a methodology to formalize the behavior of the machines composing a production line, and to automatically generate their virtual prototypes for efficient and correct plant simulation. The approach exploits assume-guarantee reasoning through contracts to model the interaction between the different components of a production line. The approach is guided by a well-known taxonomy of industrial machines and associated manufacturing processes to identify each elementary action related to a specific machine. Contracts enable to build executable models of all the machines available in the production line by using automatic synthesis. The generated models can be integrated into a state-of-the-practice industrial plant simulation software to estimate and validate the production line's behavior. The presentation of the methodology is supported by a running example based on a real production line, showing the step-by-step application of the approach to a concrete scenario.

We present a toolehain based on Docker and KubeEdge that enables containerization and orchestration of ROS-based robotic SW applications on heterogeneous and hierarchical HW architectures. The toolehain allows for verification of functional and real-time constraints through HW-in-the-loop simulation, and for automatic mapping exploration of the SW across Cloud-Server-Edge architectures. We present the results obtained for the deployment of a real case of study composed by an ORB-SLAM application combined to local/global planners with obstacle avoidance for a mobile robot navigation.

Today's factory machines are ever more connected with SCADA, MES, ERP applications as well as external systems for data analysis. Different types of network architectures must be used for this purpose. For instance, control applications at the lowest level are susceptible to delays and errors while data analysis with machine learning procedures requires to move a large amount of data without real-time constraints. Standard data formats, like Automation Markup Language (AML), have been established to document factory environment, machine placement and network deployment, however, no automatic technique is currently available in the context of Industry 4.0 to choose the best mix of network architectures according to spacial constraints, cost, and performance. We propose to fill this gap by formulating an optimization problem. First of all, spatial and communication requirements are extracted from the AML description. Then, the optimal interconnection of wired or wireless channels is obtained according to application objectives. Finally, this result is back-annotated to AML to be used in the life cycle of the production system. The proposed methodology is described through a small, but complete, smart production plant.

The advent of Industry 4.0 is making production processes every day more complicated. As such, early process validation is becoming crucial to avoid production errors thus decreasing costs. In this paper, we present an approach to validate production recipes. Initially, the recipe is specified according to the ISA-95 standard, while the production plant is described using AutomationML. These specifications are formalized into a hierarchy of assume-guarantee contracts. Each contract specifies a set of temporal behaviors, characterizing the different machines composing the production line, their actions and interaction. Then, the formal specifications provided by the contracts are systematically synthesized to automatically generate a digital twin for the production line. Finally, the digital twin is used to evaluate, and validate, both the functional and the extra-functional characteristics of the system.The methodology has been applied to validate the production of a product requiring additive manufacturing, robotic assembling and transportation.

Predictive maintenance in a manufacturing company is strategic, in order to maintain high production quality and to avoid unexpected production downtimes. In this scenario, the prediction of future machineries health status is necessary in order to plan maintenance cycles and to optimize the production. The proposed approach relies on the use of Electronic Design Automation (EDA) techniques mapped from the electronic domain to the production line domain. This paper proposes a general framework based on the EDA approach that allows to set-up a maintenance strategy by analyzing data retrieved from sensors. An MSM, is associated to each observable measurement, while a Supervisor monitors the current state of each Monitoring State Machine (MSM) by raising alerts when the monitored equipment is deviating from its normal behavior. This framework is the Digital-Twin of the plant devoted to its monitoring. It has some execution modalities ranging from online monitoring to predictive maintenance. The methodology has been applied to a mechanical transmission system showing its effectiveness.

In the context of industry 4.0, it is strategic to support factories with innovative maintenance approaches, so to avoid faults and decrease the risks of a production stop. The first step of the digitization of factories has been the collection of large amounts of data monitoring the health status of the plant. However, such data is of little use unless it is clearly correlated with information about faults occurred on the line: some faults may be sporadic, or happen only in extremely critical conditions, and thus no data may be available related to their occurrence. Artificially generating such data would force to actually damage the plant, that is of course not a viable solution. The goal of this work is to generate faulty temporal series, that reproduce the behavior of a component on the occurrence of specific faults. The innovative approach models the component of interest in Verilog-AMS (VAMS) and systematically injects the faults of interest, by keeping a direct link with the real possible cause of such faulty behavior on the plant. To prove the effectiveness of the proposed solution, the approach is applied to a direct current motor (DC motor), an electromechanical system that converts electrical energy into mechanical energy.

Pervasive computing requires to build systems every day more complex and heterogeneous. Smart devices must be able to carry on sensing and actuation alongside with computation and communication. As such, many different technologies must be packed within the same object. Digital HW and SW coexist with analog components and Micro-Electro-Mechanical systems capable of sensing and controlling the physical environment. For this reason, the design of such devices must rely on the integration of many different descriptions belonging to different design domains. The high-level of heterogeneity involved in the modeling phase of the system development makes harder the validation of the system functionality, since holistic system simulation would require the integration of many different simulators. In this article, we propose a set of automatic abstraction techniques for multi-disciplines analog components. Then, we define a scheduling strategy to integrate the execution of continuous-time analog sub-components with automatically abstracted models of the digital HW parts of the system. As a final result, the proposed methodology produces a C++ virtual platform providing a holistic simulation of complex and heterogeneous devices.

Stochastic Petri Nets (SPN)are recognized as one of the standard formalisms to model metabolic networks. They allow incorporating randomness in the model and taking into account possible fluctuations and noise due to molecule interactions in the environment. Even though some frameworks have been proposed to implement and simulate SPN (e.g., Snoopy, Monalisa), they do not allow for automatic model parameterization, which is a crucial task to identify the network configurations that lead the model to satisfy certain biological properties. We present a framework to synthesize the SPN model of a metabolic network into executable code that can be simulated through a discrete event-based simulator. The framework allows the user to formally define the network properties to be observed and to automatically extrapolate, through Assertion-based Verification (ABV), the parameter configurations that lead the network to satisfy such properties. We applied the framework to model the purine metabolism and to reproduce the metabolomics data obtained from naive lymphocytes and autoreactive T cells implicated in the induction of experimental autoimmune disorders. We show system parameterization extrapolated by the framework to reproduce the experimental results and to simulate the model under different conditions.

Stochastic Petri nets (SPN) are a form of Petri net where the transitions fire after a probabilistic and randomly determined delay. They are adopted in a wide range of applications thanks to their capability of incorporating randomness in the models and taking into account possible fluctuations and environmental noise. In Systems Biology, they are becoming a reference formalism to model metabolic networks, in which the noise due to molecule interactions in the environment plays a crucial role. Some frameworks have been proposed to implement and dynamically simulate SPN. Nevertheless, they do not allow for automatic model parametrization, which is a crucial task to identify the network configurations that lead the model to satisfy temporal properties of the model. This paper presents a framework that synthesizes the SPN models into SystemC code. The framework allows the user to formally define the network properties to be observed and to automatically extrapolate, through Assertion-based Verification (ABV), the parameter configurations that lead the network to satisfy such properties. We applied the framework to implement and simulate a complex biological network, i.e., the purine metabolism, with the aim of reproducing the metabolomics data obtained in-vitro from naive lymphocytes and autoreactive T cells implicated in the induction of experimental autoimmune disorders.

This paper analyzes a set of languages and standard used when designing industrial plants. It focuses on AutomationML and B2MML to specify respectively the architecture and the intended production of the system being designed. It also relies on the DIN 8580 standard to describe the actions performed by each machine composing the production line. Then, it outlines a methodology starting by mapping the information expressed by the analyzed languages and standards into the Assume-Guarantee Contracts formalism. It exploits contract-based design concepts to tackle the increase automation of the industrial plant design process and to enable the generation of digital twins. The approach is outlined by showing its applicability to a concrete manufacturing scenario.

The approach we present in this paper exploits assume-guarantee reasoning through contracts to model a production line, and to generate its virtual prototype for efficient and correct plant simulation. Contracts are used to model the different parts composing the line; the modeling is guided by a well-known taxonomy associating industrial machines to manufacturing processes and their elementary actions, each represented by a contract. The composition of contracts representing the actions of a machine specifies each possible manufacturing process implemented by the machine. Then, automatic synthesis from contracts is used to generate an executable model of the machines composing the plant. The generated models are finally integrated into a state-of-the-practice industrial plant simulation software to validate the execution of the production line.The entire methodology is presented by showing its step-by-step application to a concrete scenario.

Virtual platforms are a powerful support for the development and early validation of embedded SW. However, complex smart devices are built by aggregating heterogeneous components provided by different vendors, thus requiring the development of custom ad-hoc virtual platforms. Even worse, components of the underneath HW platform may belong to different design domains, that are usually expressed using a huge variety of different languages. This high degree of heterogeneity in terms of both design and specification languages must be effectively managed by the design flow so to help engineers in assembling the final system. This paper proposes a meet-in-the-middle approach to create virtual platforms of heterogeneous systems. The starting point is a set of heterogeneous models, developed by adopting the designer's favorite language and formalism. The methodology envisions the adoption of existing automatic translation and abstraction tools to automatically integrate models of components into a single homogeneous system-level executable description. The approach is supported by an analysis of the typical design flow, that leads to the definition of design domain/abstraction level taxonomies. Such taxonomies are then used to identify what characteristics would allow efficient system-level simulation, and the corresponding transformations to be applied to the starting models to achieve a “holistic” system executable representation. The benefit of such an approach is particularly evident on any kind of highly heterogeneous systems, such as smart devices. The proposed methodology has been applied to two case studies with different degrees of heterogeneity, with the goal exemplifying its adoption on concrete scenarios and to prove its effectiveness.

This paper presents a methodology that relies on Assume-Guarantee Contracts to decompose the problem of synthesizing control software for a multi-robot system. Initially, each contract describes either a component ( e.g. , a robot) or an aspect of the system. Then, the design problem is decomposed into different synthesis and verification sub-problems, allowing to tackle the complexity involved in the design process. The design problem is then recomposed by exploiting the rigorousness provided by contracts. This allows us to achieve system-level simulation capable to be used for validating the entire design. Once validated, the software synthesized during the process can be integrated into Robot Operating System (ROS) nodes and executed using state-of-the-practice packages and tools for modern robotic systems. We apply the methodology to generate a control strategy for an autonomous goods transportation system. Our results show a massive reduction of the time required to obtain automatically the control software implementing a multi-robot mission.

Smart systems are characterized by the integration in a single device of multi-domain subsystems of different technological domains, namely, analog, digital, discrete and power devices, MEMS, and power sources. Such challenges, emerging from the heterogeneous nature of the whole system, combined with the traditional challenges of digital design, directly impact on performance and on propagation delay of digital components. This article proposes a design approach to enhance the RTL model of a given digital component for the integration in smart systems with the automatic insertion of delay sensors, which can detect and correct timing failures. The article then proposes a methodology to verify such added features at system level. The augmented model is abstracted to SystemC TLM, which is automatically injected with mutants (i.e., code mutations) to emulate delays and timing failures. The resulting TLM model is finally simulated to identify timing failures and to verify the correctness of the inserted delay monitors. Experimental results demonstrate the applicability of the proposed design and verification methodology, thanks to an efficient sensor-aware abstraction methodology, by applying the flow to three complex case studies.

Development of cyber-physical systems' control algorithms usually relies on architecture-agnostic abstract models, often leading to ineffective implementations. This paper presents a technique to automatically integrate cycle-accurate models of digital HW components with continuous-time physical models. It proposes a solution to the semantic gap between the involved models of computation. Furthermore, model generation and integration for both Simulink-based proprietary environment and FMI-based portable standard are presented. The aim of such techniques is to produce cyber-physical virtual-platforms: a powerful tool to refine control algorithms up to their SW implementations on the actual HW platform.

The modelling process of Cyber-physical Systems aggregates semantics and languages tailored to different specific domains. The simulation of these complex systems involves different tools and their coupling requires computational effort. In the last few years both Academy and Industry worked toward the definition of standard interfaces able to overcome such issues. The Functional Mock-up Interface (FMI) standard emerged as one of the most promising tool to easily export and integrate heterogeneous models. However, the standard still shows some weaknesses, particularly when dealing with Functional Mock-up Units (FMUs) describing discrete-event systems. This paper explore the features of the standard to find its shortcomings when dealing with discrete models. Then, it proposes a systematic approach to fully exploit the features of the current standards to overcome such limitations. The solution is based on two concepts: (1) exposing the internal time of the FMUs, and (2) exploits the newly exposed information to implement temporal decoupling. The combination of these two concepts allows to optimize the FMUs coordination algorithms. It reduces the number synchronization points and move the simulation from cycle-accurate to transaction-accurate. The impact of these optimizations is measured on a set of benchmarks having different tread-offs of computation and control.

Functional safety is a major concern in today's networked cyber-physical systems such as connected machines, autonomous vehicles, and intelligent environments. Simulation is a well-known methodology for the assessment of functional safety. Simulation models of networked cyber-physical systems are very heterogeneous relying on digital hardware, analog hardware, and network domains. Current functional safety assessment is mainly focused on digital hardware failures while minor attention is devoted to analog hardware and not at all to the interconnecting network. We propose a holistic methodology for simulation-based safety assessment in which safety mechanisms are tested in a simulation environment reproducing the high-level behavior of digital hardware, analog hardware, and network. Also faults are tested at high abstraction level to speed up analysis.

Customizing computer vision applications for embedded systems is a common and widespread problem in the cyber-physical systems community. Such a customization means parametrizing the algorithm by considering the external environment and mapping the Software application to the heterogeneous Hardware resources by satisfying non-functional constraints like performance, power, and energy consumption. This work presents a framework for the design and simulation of embedded vision applications that integrates the OpenVX standard platform with the Robot Operating System (ROS). The paper shows how the framework has been applied to tune the ORB-SLAM application for an NVIDIA Jetson TX2 board by considering different environment contexts and different design constraints.

Digital Twin represents a simulated model of a production line which allows making analyses of future states concerning the real factory. More in details, these analyses are related to the variability of production quality, prediction of the maintenance cycle, the accurate estimation of energy consumption and other extra-functional properties of the system. This is the core of what is so called Industry 4.0. Every single node of the manufacturing process needs to be modelled as a Cyber-physical system to be able to make the mentioned analyses. However, Manufacturing simulators represent these systems with a high level of abstraction, making impossible precise analyses. In the state of the art, some solutions try to solve the problem connecting multiple domain-specific simulators, to preserve details but requiring complex co-simulation environments. This paper presents a methodology for the integration of Cyber-Physical Systems in production line simulators, avoiding these issues. The proposed solution is based on a new promising technology: the Function Mockup Interface (FMI). This standard defines an interface to exports models as blocks called Functional Mockup Units (FMUs). These FMUs can be easily integrated together composing heterogeneous systems. The methodology is composed of two steps: 1) Exporting Digital and Physical systems as different FMUs 2) Integration of the FMUs into a production line simulator. An example is used to validate our solution which clearly shows the limitations of the production line simulator without the integration of CPSs. This paper aims at producing Cyber-Physical Production Systems (CPPS) to make more accurate simulations, and hence more accurate analysis of the production line.

The amazing proliferation of communication technologies for embedded systems opens the way for completely new applications but forces designers to adopt new methodologies to meet time-to-market constraints. Computer-Aided Design (CAD) has been traditionally applied to computers and embedded systems in isolation without considering them as a global inter-connected system. The paper contributes to fill this gap by proposing 1) a communication-aware design flow for network-interconnected embedded systems and 2) a formal framework to efficiently synthesize their network aspects by formulating and solving an optimization problem. Presented case studies show the potentiality of the proposed approach to address heterogeneous scenarios, e.g., related to smart spaces up to the ever-more-mentioned Internet-of-Things.

Analog components are fundamental blocks of smart systems, as they allow a tight interaction with the environment, in terms of both sensing/actuation and communication. This impacts on the design of the overall system, and mainly on the validation phase, that thus requires the joint simulation of digital and analog aspects. In this scenario, this paper proposes the automatic conversion of analog models to C++-based languages, to remove the overhead of co-simulation with traditional virtual platform tools. The proposed methodology allows to convert a given analog description to either: 1) a fully equivalent description or 2) an abstract representation for faster simulation which models only the aspects of interest. Effectiveness and correctness have been proved on a number of case studies that highlight the effectiveness and potentiality of the proposed methodology.

Modern smart systems are usually built by implementing SW functionalities executed on HW platforms composed of both digital and analog components. Validation is mainly implemented through simulation of the functional behavior of the entire smart system modeled by a Virtual Platform. It is thus crucial to achieve fast mixed-signal simulation by removing unnecessary overhead due to synchronization between multiple tools and unimportant details. This work proposes a methodology to abstract mixed-signal systems, by integrating digital and analog components in a homogeneous virtual platform model for efficient simulation. Two main contributions are provided: 1) an automatic abstraction technique for analog components, allowing to preserve only the details meaningful for the functional behavior of the entire platform by moving complexity from simulation to generation time and 2) a novel scheduling technique that exploits temporal decoupling and synchronization of digital and analog processes, to simulate them together in a homogeneous model.

Tuning GPU applications is a very challenging task as any source-code optimization can sensibly impact performance, power, and energy consumption of the GPU device. Such an impact also depends on the GPU on which the application is run. This paper presents a suite of microbenchmarks that provides the actual characteristics of specific GPU device components (e.g., arithmetic instruction units, memories, etc.) in terms of throughput, power, and energy consumption. It shows how the suite can be combined to standard profiler information to efficiently drive the application tuning by considering the three design constraints (power, performance, energy consumption) and the characteristics of the target GPU device.

Despite analog SPICE-like simulators have reached their maturity, most of them were not originally conceived for simulating faulty circuits. With the advent of smart systems, fault testing has to deal with models encompassing both analog and digital blocks. Due to their complexity, the industry is still lacking of effective testing approaches for these analog and mixed-signal (AMS) models. The current problem is the computational time required for implementing an analog fault simulation campaign. To this end, the work presented in this paper is an automatic procedure which: 1) injects faults in an analog circuit, 2) abstracts both faulty and fault-free models from the circuit to the functional level, 3) builds an efficient fault simulation framework. The processes of fault injection, faulty model abstraction and framework generation are reported in details, as well as how simulation is carried out. This abstraction process, which preserves the faulty behaviors, allows to reach a speed-up of some orders of magnitude and thus, making feasible an extensive analog faults campaign.

Multi-discipline components introduce problems when inserted within virtual platforms of Smart Systems for functional validation. This paper lists the most common emerging problems and it proposes a set of solutions to them. It presents a set of techniques, unified in an automatic abstraction methodology, useful to achieve fast analog mixed-signal simulation even when different physical disciplines and modeling styles are combined into a single analog model. The paper makes use of a complex case study. It deals with multiple-discipline descriptions, non-electrical conservative models, non-linear equation systems, and mixed time/frequency domain models. The original component behavior has been modeled in Verilog-AMS by using electrical, mechanical and kinematic equations. Then, it has been abstracted and integrated within a virtual platform of a mixed-signal smart system for efficient functional simulation.

In the last years an inversion of trend has brought new interest to the analog domain. Its integration within modern digital designs has led to the birth of the so called Analog and Mixed-Signal (AMS) systems. Functional safety assessment of such systems must be evaluated by instrumenting both the analog and digital parts. Such an activity can be simplified if these parts can be considered as an unique layer. Based on such an idea, this work brings them to a common ground by unifying the description language. Such a process is performed through settled procedures that abstract the AMS description to a common abstraction level (behavioral) and to a homogeneous high-level language (C++). This provides a speedup of two orders of magnitude in the fault simulation of an AMS platform.

Simulation of accurate HW models is usually required to verify Embedded SW. However, heterogeneous system simulators do not easily allow it and designers must connect multiple simulators in complex co-simulation environments. This paper proposes the automatic generation of cycle-accurate Simulink blocks from the two most popular HW description languages: VHDL and Verilog. The methodology starts from an IP modeled in one of the two supported HW description languages. Then, it relies on state-of-the-art RTL models abstraction procedure to produce a functionally equivalent cycle-accurate model of the IP. Then, it proposes two alternative mapping and code-generation techniques. The first one relies on the portable FMI standard, while the other one exploits Mathworks' proprietary C MEX S-Functions. These blocks can be easily integrated within Simulink to simulate digital HW components while avoiding to build complex and computationally demanding co-simulation frameworks: a valuable feature when developing complex heterogeneous systems. A set of RTL IPs are used to compare the proposed approach to state-of-the-art co-simulation techniques. Furthermore, the experiments presented in this paper compares the two proposed alternatives to highlight their advantages and drawbacks.

Each year automotive systems are becoming smarter thanks to their enhancement with sensing, actuation and computation features. The recent advancements in the field of autonomous driving have increased even more the complexity of the electronic components used to provide such services. ISO 26262 represents the natural response to the growing concerns in terms of the functional safety of electrical safety-related systems in this area. However, if the functional safety analysis of digital devices is quite a stable methodology, the same analysis for analog components is still in its infancy. This paper aims to explore the problem of fault analysis in analog circuits and how it can be integrated into the design processes with minimum effort. The methodology is based on analog language manipulation, analog fault instrumentation and automatic abstraction. An efficient and comprehensive flow for performing such an activity is proposed and applied to complex case studies.

Smart systems represent a broad class of intelligent, miniaturized devices incorporating functionality like sensing, actuation, and control. In order to support these functions, they must include sophisticated and heterogeneous components, such as sensors and actuators, multiple power sources and storage devices, digital signal processing, and wireless connectivity. The high degree of heterogeneity typical of smart systems has a heavy impact on their design: the challenges are not in fact restricted to their functionality, but are also related to a number of extra-functional properties, including power consumption, temperature, and aging. Current simulation- or model-based design approaches do not target a smart system as a whole, but rather single domains (digital, analog, power devices, etc.) or properties. This paper tries to overcome this limitation by proposing a framework for the concurrent simulation of both functionality and such extra-functional properties. The latter are modeled as different information flows, managed by dedicated “virtual buses” and formalized through the adoption of IP-XACT. SystemC, through the support of physical and continuous time modeling provided by its analog and mixed signal extension, is used to implement both functional and extra-functional models. Experimental results show the efficiency, accuracy and modularity of the proposed approach on an example case study, in which substantial speedups with respect to standard model-based design tools go along with a very high degree of accuracy (-5%). Furthermore, the case study highlights that the proposed framework allows to easily capture at run time the mutual impact of properties, e.g., in case of power and temperature.

Simulation speed is crucial in virtual platforms, in order to enhance the design flow with early validation and design space exploration. This work tackles this challenge by focusing on two main techniques for speeding up virtual platform simulation, namely efficient data types implementation and a novel scheduling technique. Both the optimizations are obtained through code manipulation. The target language is C++ and its extensions (i.e., SystemC), that are the most widespread languages for virtual platform modeling and simulation. The optimization techniques are considered orthogonal, as they target different aspects of the simulated code. Experimental results prove the effectiveness of both the single techniques and of their combined application on complex case studies, with the result of reaching a maximum speedup of 70$\times$in the simulation of a virtual platform.

In the above paper, the location for the Arab Academy for Science and Technology was incorrect in the biography of author, Emad Ebied. The correct location is Cairo, Egypt. The correct biography is provided.

The design of distributed embedded systems is a challenging task that requires raising the level of abstraction to handle the different involved concerns. In particular, standard modeling languages and precise semantics specification are necessary to address the networking-related aspects at a high level of abstraction. The Unified Modeling Language (UML) and its MARTE profile are valid formalisms to model real-time embedded systems but they lack precise modeling elements when addressing applications and platforms forming distributed embedded systems. In this work, we formalize a coherent set of modeling elements for the design and deployment of distributed embedded systems. A novel UML profile for networking is proposed as a semantic and syntactic extension to the UML Profile for MARTE: The Network Profile.

Signal transduction is a class of cell's biological processes, which are commonly represented as highly concurrent reactive systems. In the Systems Biology community, modelling and simulation of signal transduction require overcoming issues like discrete event-based execution of complex systems, description from building blocks through composition and encapsulation, description at different levels of granularity, methods for abstraction and refinement. This paper presents a signal transduction modelling and simulation platform based on SystemC, and shows how the platform allows handling the system complexity by modelling it at different abstraction levels. The paper reports the results obtained by applying the platform to model the intracellular signalling network controlling integrin activation mediating leukocyte recruitment from the blood into the tissues.

Design of distributed embedded systems is a challenging task and it requires raising the level of abstraction to overcome the complexity of the design. In particular, modeling languages and semantic specification are necessary to address network description at high level of abstraction. Starting from this abstraction view, model manipulation is needed to explore various design alternatives and code generation is required for their simulation. In this paper, we propose the use of unified modeling language diagrams combined with a formal computational model as a key solution to specify requirements, generate design alternatives, and code for simulation. This paper proposes a formal framework and supporting tools to represent the application requirements, the library of network components, the environment description, and the rules to compose them. The framework allows to generate code for design validation by simulation and provides back annotation mechanism of the simulation results to refine the original model.

With the advent of heterogeneous multiprocessor system-on-chips (MPSoCs), hardware/software partitioning is again on the rise both in research and in product development. In this new scenario, implementing intellectual-property (IP) blocks as SW applications rather than dedicated HW is an increasing trend to fully exploit the computation power provided by the MPSoC CPUs. On the other hand, whole libraries of IP blocks are available as RTL descriptions, most of them without a corresponding high-level SW implementation. In this context, this article presents a methodology to automatically generate SW applications in C++, by starting from existing RTL IPs implemented in hardware description language (HDL). The methodology exploits an abstraction algorithm to eliminate implementation details typical of HW descriptions (such as cycle-accurate functionality and data types) to guarantee relevant performance of the generated code. The experimental results show that, in many cases, the C++ code automatically generated in a few seconds with the proposed methodology is as efficient as the corresponding code manually implemented from scratch.

With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.

Smart systems implement the leading technology advances in the context of embedded devices. Current design methodologies are not suitable to deal with tightly interacting subsystems of different technological domains, namely analog, digital, discrete and power devices, MEMS and power sources. The effects of interaction between components and with the environment must be modeled and simulated at system level to achieve high performance. Focusing on the digital domain, additional design constraints have to be considered as a result of the integration of multi-domain subsystems in a single device. The main digital design challenges, combined with those emerging from the heterogeneous nature of the whole system, directly impact on performance and on propagation delay of the digital component. This paper proposes a design approach to enhance the RTL model of a given digital component for the integration in smart systems, and a methodology to verify the added features at system-level. The design approach consists of augmenting the RTL model through the automatic insertion of delay sensors, which can detect and correct timing failures. The augmented model is abstracted to SystemC TLM and, then, mutants (i.e., code mutations for emulating timing failures) are automatically injected into the model. Experimental results demonstrate the applicability of the proposed design and verification methodology and the effectiveness of the simulation performance.

Several embedded system applications are used to control physical processes. Sensing, computation and actuation are combined thus involving a set of highly heterogeneous components, i.e., digital and analog hardware, software, energy sources, and external environment. Moreover, the growing use of networks contributes to introduce a further level of heterogeneity. All these aspects should be taken into account in the design process to find highly optimized solutions, therefore a Cyber-Physical System approach is needed. In particular, simulation is a key technique in the different design stages. However, the heterogeneity of components, together with the presence of the network, forces to adopt complex and slow co-simulation techniques to carry on the simulation of the entire system. This work aims at proposing SystemC as unified framework to model and simulate Networked Cyber-Physical Systems. Concerning the modeling of continuous-time components and a specific class of discrete-time components, the different Models of Computation provided by the Analog/Mixed-Signal (AMS) extension of SystemC are used. Regarding the network, SystemC and the SystemC Network Simulation Library are used to model communications at different abstraction levels. The accuracy and speed of different simulation alternatives are compared by the application to a networked control system.

Electrical energy systems (EESs) are systems which consume, generate, distribute and store energy at various scales. This paper presents a modeling and simulation framework that uses principles borrowed from the system-level simulation of digital systems and extends them to the case of EESs. The framework relies on open-source standards such as SystemC (and its Analog and Mixed-Signal extensions) for simulation, and IP-XACT for interface definition.

Transaction-level modeling (TLM) has become the de-facto reference modeling style for system-level design and verification of embedded systems. It allows designers to implement high-level communication protocols for simulations up to 1000 × faster than at register-transfer level (RTL). To guarantee interoperability between TLM IP suppliers and users, designers implement the TLM communication protocols by relying on a reference standard, such as the standard OSCI for SystemC TLM. Functional correctness of such protocols as well as their compliance to the reference TLM standard are usually verified through user-defined testbenches, whose high quality and completeness play a key role for an efficient TLM design and verification flow. This article presents a methodology to apply mutation analysis, a technique applied in literature for SW testing, for measuring the testbench quality in verifying TLM protocols. In particular, the methodology aims at (i) qualifying the testbenches by considering both the TLM protocol correctness and their compliance to a defined standard (i.e., OSCI TLM), (ii) optimizing the simulation time during mutation analysis by avoiding mutation redundancies, and (iii) driving the designers in the testbench improvement. Experimental results on benchmarks of different complexity and architectural characteristics are reported to analyze the methodology applicability.

We present a method to automatically generate a synthesizable C++ specification from the given RTL design of an IP block, by abstracting away most of its micro-architectural characteristics while preserving its functionality. The goal is twofold: recover the IP block specification for system-level design, and enable the derivation of more optimized implementations through high-level synthesis. The C++ specification can be generated with different interfaces thus allowing the IP model to be reused across different system platforms. Experimental results show that the proposed approach not only enhances the reusability of the recovered IP block but also unveils a richer design space to explore.

General purpose graphics processing units (GP-GPUs) have recently been explored as a new computing paradigm for accelerating compute-intensive EDA applications. Such massively parallel architectures have been applied in accelerating the simulation of digital designs during several phases of their development - corresponding to different abstraction levels, specifically: (i) gate-level netlist descriptions, (ii) register-transfer level and (iii) transaction-level descriptions. This embedded tutorial presents a comprehensive analysis of the best results obtained by adopting GP-GPUs in all these EDA applications.

The behavior of Networked Embedded Systems (NES) is not only driven by network components but also by the surrounding environment. To verify the correct behavior of such systems, different tests should be performed under different environmental conditions. The complexity and expense of testing such systems in real environments leads us to propose a simulation-based approach to tackle this problem. In this work, we propose UML-based methodology and a framework for modeling NES applications together with the environment and a mechanism to automatically generate simulation code for design verification. The approach is supported by a novel UML profile and a set of tools for simulation code generation.

Fault injection is fundamental to evaluate the dependability of embedded software. Analyzing the interaction between the software and hardware components when hardware faults occur is efficient, but it is only possible once physical prototypes are available. On the other hand, fault injection on Hardware Description Language (HDL) models is a common practice that can significantly improve the verification phases, but HDL simulation speed constitutes a bottleneck of the design flow. In such a context, executing software on a virtual CPU providing fault-injection capabilities allows engineers to anticipate Embedded Software (ESW) dependability analysis at an earlier design stage. Thus, we present a non-intrusive approach that offers high speed for simulating hardware faults affecting CPU behaviors. This is obtained through dynamic translation of ESW binary code. In this work, hardware fault models (i.e., stuck-at, transient and delay faults) have been abstracted to an instruction-accurate CPU emulator without losing quality for ESW dependability analysis. Experimental results proves both the efficiency and effectiveness of the proposed approach.

Designers are more and more forced to define innovative models and methodologies for managing integration of heterogeneous components and heterogeneous Chip Multiprocessors (CMPs) in modern embedded systems. In this context, component-based design seems the more promising approach, but it suffers from the lack of a widely adopted Model of Computation (MoC) able to capture component heterogeneity. This paper proposes univerCM, a new model of computation based on the Heterogeneous Intermediate Format (HIF) with the aim of supporting bottom-up design and system integration from a set of heterogeneous components. HW and SW components can be described by means of different languages and according to different MoCs, toward a uniform intermediate description based on a rigorous semantics. A mapping from univerCM to SystemC is proposed then to obtain a homogeneous description intended for fast simulation, that can be also used as starting point for CMP design flows. Experimental results show the effectiveness of univerCM in managing system heterogeneity.

IP core integration into an embedded platform implies the implementation of a customized device driver complying with both the IP communication protocol and the CPU organization (single processor, SMP, AMP). Such a close dependence between driver and platform organization makes reuse of already existing device drivers very hard. Designers are forced to manually customize the driver code to any different organization of the target platform. This results in a very time-consuming and error-prone task. In this paper, we propose a methodology to semi-automatically generate customized device drivers, thus allowing a more rapid embedded platform development. The methodology exploits the testbench provided with the RTL IP module for extracting the formal model of the IP communication protocol. Then, a taxonomy of device drivers based on the CPU organization allows the system to determine the characteristics of the target platform and to obtain a template of the device driver code. This requires some manual support to identify the target architecture and to generate the desired device driver functionality. The template is used then to automatically generate drivers compliant with 1) the CPU organization, 2) the use in a simulated or in a real platform, 3) the interrupt support, 4) the operating system, 5) the I/O architecture, and 6) possible parallel execution. The proposed methodology has been successfully tested on a family of embedded platforms with different CPU organizations.

The increasing prevalence of timing-related failures in integrated circuits makes delay-fault test generation extremely important in the design flow. However, delay test generation is a complex and computational-intensive activity, and it is feasible relatively later in the design process because of the need for low-level implementation details. In contrast, TLM system models are available from the early phases of the design process, but they lack the low-level details needed for delay test generation. In this paper, we first propose a high-level fault model capable of representing transition delay faults at TLM through mutation analysis. We then propose a test-generation methodology centered around this fault model. Its purpose is to reduce the complexity of test generation for transition delay faults for non-scan circuits. This is achieved by exploiting TLM simulation speed and early availability of TLM models in the design process. Experimental results highlight the effectiveness of the proposed methodology by achieving a speedup in CPU time in the range of one order of magnitude, and a 10% average increase in fault coverage.

SystemC is a widespread language for HW/SW system simulation and design exploration, and thus a key development platform in embedded system design. However, the growing complexity of SoC designs is having an impact on simulation performance, leading to limited SoC exploration potential, which in turns affects development and verification schedules and time-to-market for new designs. Previous efforts have attempted to parallelize SystemC simulation, targeting both multiprocessors and GPUs. However, for practical designs, those approaches fall far short of satisfactory performance. This paper proposes SAGA, a novel simulation approach that fully exploits the intrinsic parallelism of RTL SystemC descriptions, targeting GPU platforms. By limiting synchronization events with ad-hoc static scheduling and separate independent dataflows, we shows that we can simulate complex SystemC descriptions up to 16 times faster than traditional simulators.

This work proposes an advanced methodology based on an open source virtual prototyping framework for verification of complex Heterogeneous Embedded Systems (HES). It supports early rapid modelling of complex HES through smooth refinements, an open interface based on IP-XACT extensions for secure composition of HES components, and automatic testbench generation over different abstraction levels.

This paper presents FAST-GP, a framework for functional verification of RTL designs, which is based on fault injection and parallel simulation on GP-GPUs. Given a fault model, the framework translates the RTL code into an injected C code targeting NVIDIA GPUs, thus allowing a very fast parallel automatic test pattern generation and fault simulation. The paper compares different configurations of the framework to better exploit the architectural characteristics of such GP-GPUs (such as thread synchronization, branch divergence, etc.) by considering the architectural characteristics of the RTL design under verification (i.e., complexity, size, number of injected faults, etc.). Experimental results have been conducted by applying the framework to different designs, in order to prove the methodology effectiveness.

Network design in distributed embedded applications is a novel challenging task which requires 1) the extraction of communication requirements from application specification and 2) the choice of channels and protocols connecting physical nodes. These issues are faced in the paper by adopting UML/MARTE as specification front-end and repository of refined versions of the model obtained by both simulation and analytical exploration of the design space. The emphasis is on using standard UML/MARTE elements for the description of networked embedded systems to allow re-use, tool interoperability and documentation generation. The approach is explained on a case study related to building automation.

Assertion-based verification (ABV) is more and more used for verification of embedded systems concerning both HW and SW parts. However, ABV methodologies and tools do not apply to HW and SW components in the same way: for HW components, both static ABV and dynamic ABV are widely used; on the contrary, SW components are traditionally verified by means of static ABV, because dynamic approaches are based on simulation assumptions which could not be true during execution of general embedded SW and which cannot be controlled by the assertion language. This paper proposes to exploit model-driven design for guaranteeing such simulation assumptions. Then, it describes an ABV framework for embedded SW, that automatically synthesizes assertion checkers to verify the embedded SW accordingly to the simulation assumptions.

Verification of real time embedded systems at high level of abstraction is a challenging task that requires the simulation of the system and the checking of its timing and functional properties as well as constraints. The paper presents a methodology which starts from UML sequence diagrams with MARTE timing constraints and generates a SystemC/TLM model with checkers. The execution of the model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. The application of the methodology to the design of a wireless sensor node shows the validity of the approach and its simulation overhead.

Assertion-based verification (ABV) affirmed as an effective methodology for functional verification, i.e., design specification conformance, of embedded systems. Academia and industry have throughly investigated formal ABV for high-budget or safety-critical hardware and software projects, while the scalability of dynamic ABV has led to the introduction of standard languages and commercial tools addressing hardware design verification, emulation, and silicon debug. However, up to now, there were only limited studies concerning the application of dynamic ABV to embedded-software design and verification flow. We propose an analysis aiming to bridge such a gap. In particular, we illustrate how dynamic ABV can integrate and improve the various stages of the embedded-software verification flow. The analysis leads us to develop a comprehensive ABV environment that integrates the still missing automatic synthesis of executable checkers for embedded software. Experiments show that the proposed environment reduces the verification-team efforts and makes dynamic ABV practical for embedded-software design.

Verification of real time embedded systems is becoming more and more complex in terms of maintaining the code size and keeping equivalence between the specification. It requires the simulation of the system and the checking of its timing and functional properties as well as constraints. The paper presents a methodology which starts from UML sequence diagrams with MARTE timing constraints and generates a VHDL model with checkers. The simulation of the model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. The application of the methodology to the design of a wireless sensor node shows the validity of the approach and its simulation overhead.

Verification is increasingly becoming the bottleneck in designing digital systems. In fact, most of the verification cycle is not spent on detecting the occurrences of errors but on debugging, consisting of locating and correcting the errors. However, automated design-error debug, especially at the system-level, has received far less attention than error detection. Current paper presents an automated approach to correcting system-level designs. We propose dynamic-slicing and location-ranking-based method for accurately pinpointing the error locations combined with a dedicated set of mutation operators for automatically proposing corrections to the errors. In order to validate the approach, experiments on the Siemens benchmark set have been carried out. The experiments show that the proposed method is able to correct three times more errors compared to the state-of-the-art mutation-based correction methods while examining fewer mutants.

Heterogeneous multicore system-on-chips (MPSoCs) provide many degrees of freedom to map functionalities on either SW and HW components. In this scenario, enabling the remapping of HW IPs as SW routines allows to fully exploit the computation power and flexibility provided by heterogeneous MPSoCs. On the other hand, reuse of existent IP cores is the key strategy to explore this large design space in a reasonable amount of time and to reduce the error risk during the MPSoC design flow. A methodology for automatic generation of parallel SW code taking into account these aspects is currently missing. This paper aims at overcoming this limitation, by presenting a methodology to automatically generate parallel SW IPs starting from existent RTL IP models.

HW-SW partitioning is a key problem in HW-SW code sign of embedded systems studied extensively in the past. All proposed approaches are top down flows, that start from a homogeneous formal specification of the system and determine an optimal partitioning. Thus, the proposed techniques do not exploit reuse nor reconsider the HWSW partitioning of an already designed platform. This paper proposes an extension of traditional flows that allows reuse and automatic generation of components and interfaces. The final flow has been applied to a complex industrial platform to prove the effectiveness and the advantages of the proposed approach.

Different fault injection techniques based on simulation have been proposed in the past for functional verification of register transfer level (RTL) IP models. They allow designers to model any type of fault and provide the quality of test patterns through the fault coverage estimation. Nevertheless, the low speed of such a cycle-accurate RTL simulation involves a trade-off between the simulation time and the achieved fault coverage. On the other hand, Transaction-level modeling (TLM) allows a simulation speed-up up to 1000x with respect to RTL. This paper presents a methodology to accelerate RTL fault simulation through automatic RTL-to-TLM abstraction. The methodology abstracts injected RTL models into equivalent injected TLM models thus allowing a very fast automatic test pattern generation at TLM level. The paper shows how the generated TLM test patterns can be automatically synthesized into RTL test patterns by exploiting the structural information of the RTL model extracted during the abstraction process. Experimental results have been applied to several designs of different size and complexity to show the methodology effectiveness.

We present an approach for optimization of assertion placement in time-constrained HW/SW modules for detection of errors due to transient and intermittent faults. During the design phases, these assertions have to be inserted into the executable code and, hence, will always be executed with the corresponding code branches. As the result, they can significantly increase execution time of a module, in particular, contributing to a much longer execution of the worst case, and cause deadline misses. Assertions have different characteristics such as tightness (or "local error coverage") and execution latency. Taking into account these properties can increase efficiency of assertion checks in time-constrained embedded HW/SW modules. We have developed a design optimization framework, which (1) identifies candidate locations for assertions, (2) associates a candidate assertion to each location, and (3) selects a set of assertions in terms of performance degradation and assertion tightness. Experimental results have shown the efficiency of the proposed techniques.

The paper presents a design methodology for distributed applications of networked embedded systems. The original contribution is the joint perspective on communication aspects and dependability. The methodology allows to model the dependability requirements of the application under design and the degree of dependability of involved components, like nodes, communication protocols, and channels. By assessing the dependability degree of a candidate solution, the methodology allows to iterate the synthesis process until requirements are met. The effectiveness of the proposed design flow is shown by an actual case study.

State-of-the-art approaches for testing of system-level design of embedded systems generally work at source-code level, thus they require an implementation of the system to be tested. For this reason, they cannot be applied in the context of model-driven design, where code is available only at end of the design process. Moreover, traditional approaches based on combined concrete and symbolic execution (concolic) suffer two main drawbacks: they are limited in width and depth of the search and not corner-cases oriented. To address such limitations, this paper presents a concolic testing approach for model-driven design of embedded systems. It explores a model of the system, i.e., the extended finite state machine (EFSM), and it relies on weight-oriented analysis of the EFSM paths to achieve high controllability of EFSM transitions, by interleaving longrange concrete approach with symbolic multi-level backjumping strategy. The experimental evaluation on several case studies demonstrates the competitiveness of the proposed approach, which achieves higher transition and instruction coverage than other approaches in significantly reduced time.

Network design in distributed embedded applications is a novel challenging task which requires 1) the extraction of communication requirements from application specification and 2) the choice of a suitable communication infrastructure among physical nodes. These issues are faced in the paper by adopting a middleware-based design flow in which the middleware is also modeled and simulated as a component of the whole system. This way, the communication requirements are extracted from middleware calls and network design consists in the choice among different actual middleware implementations whose communication impact has been characterized. Experimental results on actual boards show the accuracy of the proposed methodology.

Transaction-level modeling (TLM) is the most promising technique to deal with the increasing complexity of modern embedded systems. However, modeling a complex system completely at transaction level could be inconvenient when IP cores are available on the market, since they are usually modeled at register transfer level (RTL). In this context, modeling and verification methodologies based on transactors allow designers to reuse RTL IPs into TLM-RTL mixed designs, thus guaranteeing a considerable saving of time. Practical advantages of such an approach are evident, but mixed TLM-RTL designs cannot completely provide the well-known effectiveness in terms of simulation speed provided by TLM. This paper presents a methodology to automatically abstract RTL IPs into equivalent TLM descriptions. To do that, the paper first proposes a formal definition of equivalence based on events, showing how such a definition can be applied to prove the correctness of a code manipulation methodology, such as code abstraction. Then, the paper proposes a technique to automatically abstract RTL IPs into TLM descriptions. Finally, the paper shows that the TLM descriptions obtained by applying the proposed technique are correct by construction, relying on the given definition of event-based equivalence. A set of experimental results is reported to confirm the effectiveness of the methodology.

High performance provided by multi-processor System-on-Chips (MPSoCs) often induces designers to choose customized processors to execute specific functions rather than using dedicated hardware. On the other hand, reuse of pre-designed and pre-verified IP cores is the key strategy to meet time-to-market while at the same time reducing the error risk during the development of MPSoC designs. In this context, it becomes convenient to translate an existent RTL IP description, originally dedicated to implement an HW component, into pure SW code (i.e., C/C++) to be executed by one or more processors of the MPSoC. This work proposes a methodology to automatically generate SW code by abstracting RTL IP models implemented in hardware description language (HDL). The methodology exploits an abstraction algorithm to eliminate many implementation details typical of the HW descriptions, in order to improve the performance of the generated code.

Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.

The paper tackles the problem of property qualification focusing in particular on the identification of vacuous properties. It proposes a methodology based on a combination of dynamic and static techniques that, given a set of properties defined to check the correctness of a design implementation, performs vacuity detection. Existing approaches for vacuity checking are as complex as model checking, and they require to define and model check further properties, thus increasing the verification time. Moreover, for some formulae they fail to detect vacuity, as for example in case of tautology. These problems are overcome by our approach. It is based on mutation analysis, thus, it does not require the definition of new properties granting a speed-up of the vacuity analysis process. Moreover, it provides highly accurate vacuity alerts which capture also propositional and temporal tautologies.

The paper addresses the design-space exploration of network alternatives for complex distributed systems of embedded devices, e.g., for smart power grid or telecommunication services. While past research mainly provided efficient programming abstractions and HW/SW simulation tools, this work introduces the network perspective in the verification of different design solutions (e.g., different task decomposition and assignment to network nodes). To do that, network simulation capability has been added to the so-called Abstract Middleware Environment and its effectiveness has been shown experimentally through the design of a wireless sensor network application taken from a real-world case study.

The paper proposes DDPSL (Drag and Drop PSL) a template library and a tool which simplifies the definition of PSL (Property Specification Language) formal properties by exploiting PSL-based templates. DDPSL allows users not expert in formal methods to define PSL properties by dragging and dropping logical and temporal operators, and variables from the design under verification (DUV) into predefined templates. Moreover, confident users or experts can extend the set of templates, reducing the effort required for formalizing complex properties. From the methodological point of view, DDPSL combines the advantages of both Open Verification Library (OVL) and PSL. Note that the templates are characterized by a parametric interface that separates the formal definition from its semantics, as provided by OVL. Moreover, the adoption of PSL as reference language guarantees the expressiveness of popular temporal logics such as Linear Temporal Logic (LTL) and Computational Tree Logic (CTL), which, on the contrary, are not fully supported by OVL. DDPSL has been successfully used to define properties for verifying an embedded application running on the microcontroller of an industrial oven.

Transaction-level modeling (TLM) is the leading design style to deal with the increasing complexity of modern embedded systems. TLM provides designers with high-level interfaces and communication protocols for abstract modeling and efficient simulation of system platforms. The Open SystemC Initiative (OSCI) has recently released the TLM-2.0 standard for facilitating the interchange of models between suppliers and users, and thus encouraging the use of virtual platforms for fast simulation prior to the availability of register-transfer level (RTL) code. On the other hand, verification of TLM IPs still relies on simulation-based techniques since formal verification methodologies (such as model checking) and tools are not mature enough to be applied at TLM level. In this paper, we propose a methodology to apply existing RTL model checkers for verifying TLM IPs. The methodology relies on the automatic synthesis of the TLM IP models into equivalent RTL descriptions, in order to verify the TLM properties through the equivalent RTL model of the IPs.

This article presents a methodology for the design of Networked Embedded Systems (NESs), which extends Transaction Level Modeling (TLM) to perform system/network design-space exploration. As a result, a new design dimension is added to the traditional TLM refinement process to represent network configuration alternatives. Each network configuration can be used to drive both architecture exploration and system validation after each refinement step. A system/network simulation taxonomy is investigated aiming at precisely identifying the role of cosimulation in system/network design-space exploration. Furthermore, a general criterion to map functionalities to system and network models is presented. As a case study, the proposed methodology is applied to the design of a Voice-over-IP client.

The topic will cover the use of functional qualification for measuring the quality of functional verification of TLM models. Functional qualification is based on the theory of mutation analysis but considers a mutation to have been killed only if a test case fails. A mutation model of TLM behaviors is proposed to qualify a verification environment based on both testcases and assertions. The presentation describes at first the theoretic aspects of this topic and then it focuses on its application to real cases by using actual EDA tools, thus showing advantages and limitations of the application of mutation analysis to TLM.

The generation of device drivers is a very time consuming and error prone activity. All the strategies proposed up to now to simplify this operation require a manual, even formal, specification of the device driver functionalities. In the system-level design, IP functionalities are tested by using testbenches, implemented to contain the communication protocols to correctly interact with the device. The aim of this paper is to present a methodology to automatically generate device drivers from the testbench of any RTL IP. The only manual step required is to tag the states corresponding to the different device functionalities. The Extended Finite State Machines (EFSMs) are then used to create a correct-by-construction two-level device driver: the lower level deals with architectural choices, while the higher one is derived from the EFSMs and it implements the communication protocols. The effectiveness of this methodology has been proved by applying it to a platform provided by STMicroelectronics.

This paper presents an accurate and scalable implementation of an energy-aware simulator for wireless sensor networks (WSN's). Scalability and accuracy have been achieved through an energy-aware instrumentation of the Instruction Set Simulator of node's microcontroller and a functional SystemC TLM model of the radio module implementing the IEEE 802.15.4 protocol. The framework allows to execute actual software and to evaluate accurately its effect on the network lifetime. We first validate energy estimation results against a working hardware prototype of a wireless sensor node. The methodology, compared against state-of-the-art simulators such as NS-2, represents a flexible and scalable solution for fast and accurate prototyping of WSN software.

The extreme heterogeneity of networked embedded platforms makes both design and reuse of applications really hard. These facts decrease portability. A middleware is the software layer that allows to abstract the actual characteristics of each embedded platform. Using a middleware decreases the difficulty in designing applications, but programming for different middlewares is still a barrier to portability. This paper presents a design methodology based on an abstract middleware environment that allows to abstract even the services provided. This is gained by allowing the designer to smoothly move across different design paradigms. As a proof, the paper shows how to mix and exchange applications between tuple-space and message-oriented based middleware environments.

The effectiveness and the efficiency of functional ATPGs based on deterministic strategies is influenced by the computational model adopted to represent the design under test. In this context the extended finite state machine (EFSM) is a valuable model which reduces the risk of state explosion preserving relevant features of more traditional FSMs. This paper. defines a particular variant of EFSMs to manage properly both synchronous and asynchronous modules in a uniform way, and then it proposes theoretical basis to perform their composition by bounding state and transition growth. The aim of composition is to improve functional ATPG whose effectiveness and efficiency may be limited when separate EFSMs are used to model the design under test. Experimental results confirm this conjecture.

Dependability is becoming a key design aspect of today networked embedded systems (NES's) due to their increasing application to safety-critical tasks. Dependability evaluation must be based on modelling and simulation of faulty application behaviors, which must be related to faulty NES behaviors under actual defects. However, NES's behave differently from traditional embedded systems when testing activities are performed on them. In particular, issues arise on the definition of correct behavior, on the best point to observe it, and on the temporal properties of the faults to be injected. The paper describes these issues, discusses some possible solutions and presents a new time-varying network-based fault model to represent failures in a more abstract and efficient way. Finally, the fault model has been used to support the design of a network-based control application where packet losses, end-to-end delay and signal distortion must be carefully controlled.

The paper proposes a comprehensive methodology for property qualification based on a combination of dynamic and static techniques. In particular, given a set of properties defined to check the correctness of a design implementation, the methodology first evaluates property coverage, property overspecification, and it identifies vacuous properties. This is commonly performed by exploiting mutation analysis and automatic testbenches generation, i.e., dynamic strategies. This phase allows us to quickly evaluate the quality of properties with respect to the use of formal approaches. Then, a second phase, based on model checking, is applied to the restricted number of situations, where the dynamic approach is not exhaustive. Experimental results show the effectiveness and efficiency of the proposed methodology.

The literature does not report a complete design methodology for WSN applications integrating all these aspects. The proposed methodology allows programmers to write WSN applications by using the system description language SystemC and the Abstract Middleware Environment (AME) framework for fast sim

Cosimulation strategies allow us to simulate and verify HW/SW embedded systems before the real platform is available. In this field, there is a large variety of approaches that rely on different communication mechanisms to implement an efficient interface between the SW and the HW simulators. However, the literature lacks a comprehensive methodology which addresses the need for integrating and synchronizing heterogeneous simulators, like, for example, the SystemC simulation kernel for HW modules and an instruction set simulator for SW applications, without being intrusive for the HW and SW descriptions involved in the simulation. In this context, this article presents, compares, and integrates in a system-level framework two different co-simulation strategies for modeling, analyzing, and validating the performance of a HW/SW embedded system. Moreover, for both of them, a mechanism is proposed to provide an accurate time synchronization of the HW/SW communication. The first strategy is intended to provide an early cosimulation environment where HW/SW interaction can be validated without involving the operating system. The communication is implemented between a single SW task and a SystemC description of an HW module by exploiting the features of the remote debugging interface of a debugger (the GNU GDB), and by modifying the SystemC simulation kernel. On the other hand, the second strategy is intended to be used in further development steps, when the operating system is introduced to validate the cosimulation between HW modules and multitasking SW applications. In this approach, the communication is implemented via interrupts by using the features offered by the operating system. Experimental results are reported on two different case studies to analyze and compare the effectiveness of both the approaches.

Transaction Level Modeling (TLM) is an emerging design practice for overcoming increasing design complexity. It aims at simplifying the design flow of embedded systems by designing and verifying a system at different abstraction levels. In this context, transactors play a fundamental role since they allow communication between the system components, implemented at different abstraction levels. Reuse of RTL IPs into TLM systems is a meaningful example of key advantage guaranteed by exploiting transactors. Nevertheless, transactors implementation is still manual, tedious and error-prone, and the effort spent to verify their correctness often overcomes the benefits of the TLM-based design flow. In this paper we present a methodology to automatically generate transactors for RTL IPs. We show how the transactor code can be automatically generated by exploiting the testbench of any RTL IP.

Mutation analysis is a widely-adopted strategy in software testing with two main purposes: measuring the quality of test suites, and identifying redundant code in programs. Similar approaches are applied in hardware verification and testing too, especially at RTL or gate level, where mutants are generally referred as faults, and mutation analysis is performed by means of fault modeling and fault simulation. However, in modern embedded systems there is a close integration between HW and SW parts, and verification strategies should be applied early in the design flow. This requires the definition of new mutation analysis-based strategies that work at system level, where HW and SW functionalities are not partitioned yet. In this context, the paper proposes a mutation model for perturbing transaction level modeling (TLM) SystemC descriptions. In particular, the main constructs provided by the SystemC TLM 2.0 library have been analyzed, and a set of mutants is proposed to perturb the primitives related to the TLM communication interfaces.

Next-generation networked embedded systems pose new challenges in the design and simulation domains. System design choices may affect the network behavior and network design choices may impact on the system design. For this reason, it is important -at the early stages of the design flow- to model and simulate not only the system under design, but also the heterogeneous networked environment in which it operates. For this purpose, we have exploited a modeling language traditionally used for System design -SystemC- to build a system/network simulator named SystemC Network Simulation Library (SCNSL). This library allows to model network scenarios in which different kinds of nodes, or nodes described at different abstraction levels, interact together. The use of SystemC as unique tool has the advantage that HW, SW, and network can be jointly designed, validated and refined. As a case study, the proposed tool has been used to simulate a sensor network application and it has been compared with NS-2, a well-known network simulator; SCNSL shows nearly two-order-magnitude speed up with TLM modeling and about the same performance as NS-2 with a mixed TLM/RTL scenario. The simulator is partially available to the community at http://sourceforge.net/projects/scnsl/.

In this paper we present an energy-aware framework for the design of wireless sensor networks, based on a hardware/software/network co-simulation strategy. The framework enables fast development and optimization of software power management policies, since it allows to run real software that can be easily ported on target hardware nodes. The capabilities of the simulation framework have been stressed by comparing different power management strategies, exploring their power-performance trade-offs and their effectiveness in various network conditions.

Vacuum cleaning is a mandatory process when an implementation is verified with respect to a specification modeled by means of formal properties. In fact, vacuum cleaning looks for properties that, passing vacuously (e.g., an implication whose antecedent is always false), may lead verification engineers to a false sense of safety. Current approaches to vacuum cleaning, generally, exploit formal methods to provide an interesting witness proving that a property does not pass vacuously. However, such approaches are as complex as model checking, and they require to define and model check further properties, thus increasing the verification time. This paper proposes an alternative approach, based on fault simulation, that requires neither the definition of new properties, nor the use of model checking. Experimental results show the high efficiency of this approach.

In transaction-level modeling (TLM), verification methodologies based on transactions allow testbenches, properties, and IP cores in mixed TL-RTL designs to be reused. However, no papers in the literature analyze the effectiveness of transaction-based verification (TBV) in comparison to the more traditional RTL approach. The first contribution of this article is the introduction of a functional-fault-model-based methodology for demonstrating the effectiveness of reuse through TBV. A second contribution is the introduction of a similar methodology for efficient property checking which identifies and removes redundant properties prior to assertion-based verification or model checking.

This paper addresses the problem of modeling and simulating large set of heterogeneous networked embedded systems which cooperate to build cost-efficient, reliable, secure and scalable applications. The purpose of this task is an application-driven top-down design flow which starts from application requirements and then progressively decides the general architecture of the system and the type and structure of its HW, SW and network components. In the past, a considerable research effort has been done to create specific tools for each design domain - software, hardware and network - and to integrate them for data exchange between models and their joint simulation. However the advantages and drawbacks of different combinations of tools in the various stages of the design flow have not been discussed. The paper describes and discusses how to combine different modeling tools to provide different modeling and simulation alternatives for the design of networked embedded systems devoted to complex distributed applications. The problem is faced both theoretically and practically with a real application derived from a European project

Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems. However, its introduction arouses a new challenge for designers and verification engineers, since there are no mature tools to automatically synthesize an RTL implementation from a transaction-level (TL) design, thus manual refinements are mandatory. In this context, the paper presents an incremental assertion-based verification (ABV) methodology to check the correctness of the TL-to-RTL refinement. The methodology relies on reusing assertions and already checked code, and it is guided by an assertion coverage metrics

Separation of HW and SW design flows represents a critical aspect in the development of embedded systems. Co-verification becomes necessary, thus implying the development of complex co-simulation strategies. This paper presents a refinement flow that delays as much as possible the separation between HW and SW concurrent entities (threads), allowing their differentiation, but preserving an homogeneous simulation environment. The approach relies on SystemC as the unique reference language. However, SystemC threads, corresponding to the SW application, are simulated outside the control of the SystemC simulation kernel to exploit the typical features of multi-threading real-time operating systems running on embedded systems. On the contrary HW threads maintain the original simulation semantics of SystemC. This allows designers to effectively tune the SW application before HW/SW partitioning, leaving to an automatic procedure the SW generation, thus avoiding error-prone and time-consuming manual conversions

The paper focuses on the design of networked embedded systems which cooperate to provide complex distributed applications. A milestone in the effort of simplifying the implementation of such applications has been the introduction of a service layer, named middleware, which abstracts from the peculiarities of the operating system and HW components. However, the presence of the middleware has not been yet introduced in the design flow as an explicit dimension. This work presents an abstract model of middleware supporting different programming paradigms; it can be used as component in the design flow and allows to simulate and develop the application without doing premature assumptions on the actual HW/SW platform. At the end of the design flow the abstract middleware can be mapped to an actual middleware. The methodology has been analyzed both theoretically and practically with the actual application on a wireless sensor network

The always increasing complexity of digital system is overcome in design flows based on transaction level modeling (TLM) by designing and verifying the system at different abstraction levels. The design implementation starts from a TLM high-level description and, following a top- down approach, it is refined towards a corresponding RTL model. However, the bottom-up approach is also adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system. In this context, proving the equivalence between a model and its refined or abstracted version is still an open problem. In fact, traditional equivalence definitions and formal equivalence checking methodologies presented in the literature cannot be applied due to the very different internal characteristics of the models, including structure organization and timing. Targeting this topic, the paper presents a formal definition of equivalence based on events, and then, it shows how such a definition can be used for proving the equivalence in the RTL vs. TLM context, without requiring timing or structural similarities between the modules to be compared. Finally, the paper presents a practical use of the proposed theory, by proving the correctness of a methodology that automatically abstracts RTL IPs towards TLM implementations.

Verification engineers cannot guarantee the correctness of the system implementation by model checking if the set of proven properties is incomplete. However, the use of model checking lacks widely accepted coverage metrics to evaluate the property completeness. The already existing metrics are based on time-consuming formal approaches that cannot be efficiently applied to medium/large systems. In this context, the paper proposes a coverage methodology based on a combination of static and dynamic verification that allows us to reduce the evaluation time with respect to pure formal approaches. The joining point between static and dynamic verification is represented by a fault model targeting functional descriptions. Functional fault simulation and dynamic automatic test pattern generation are used to quickly estimate the capability of properties in detecting functional faults. This provides a first estimation of the property completeness. Then, if necessary, model checking is used to complete the analysis, avoiding the underestimation of the property coverage that can be obtained due to the lack of exhaustiveness of dynamic verification. The proposed approach is theoretically founded and its effectiveness is compared with already existing techniques. In addition, experimental results to confirm the theoretical results are provided

Transaction level modeling (TLM) is becoming a usual practice for simplifying system-level design and architecture exploration. It allows the designers to focus on the functionality of the design, while abstracting away implementation details that will be added at lower abstraction levels. However, moving from transaction level to RTL requires redefining TLM test benches and assertions. Such a wasteful and error prone conversion can be avoided by adopting transactor-based verification (TBV). Many recent works adopt this strategy to propose verification methodologies that allow: (1) mixing TLM and RTL components; and (2) reusing TLM assertions and test benches at RTL. Even if practical advantages of such an approach are evident, there are no papers in the literature that evaluate the effectiveness of the TBV compared to a more traditional RTL verification strategy. This paper is intended to fill in the gap. It theoretically compares the quality of the TBV towards the rewriting of assertions and test benches at RTL with respect to both fault coverage and assertion coverage

The paper describes a functional ATPG that explores the DUT state space by exploiting an easy-to-traverse extended FSM model. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the EFSM

Modular design is an important requirement in modern embedded system design flows because of the widespread acceptance of new paradigms such as IP core reuse and platform-based design. Co-simulation frameworks must thus support modular design, since programmable devices, ad-hoc HW components, and the interconnect infrastructure must be easily interchangeable in order to allow design exploration while keeping the SW portion unchanged or only marginally changed. The proposed co-simulation framework implements such a modular approach to co-simulation by means of a novel paradigm in which HW models can be modified on the fly by keeping the SW parts unchanged. This is achieved through an ISS-centric co-simulation strategy in which modularity is provided in terms of (i) the replacement of HW components thanks to the use of a common interface based on the device address space, or (ii) the use of different ISS's, thanks to a re-configurable simulator. We demonstrate our approach onto an industrial-strength embedded application, showing that the proposed co-simulation strategy provides both high speed and accuracy.

Transaction-level modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems. However, modeling a complex system completely at transaction level (TL) could be inconvenient when IP cores are available on the market, usually modeled at RT level. In this context, modeling and verification methodologies based on transactors allow one to reuse RTL IP-cores in TL-RTL mixed designs, thus guaranteeing a considerable saving of time. Even if practical advantages of such an approach are evident, mixed TL-RTL designs cannot completely benefit from the well-known effectiveness provided by TLM. Thus, this paper proposes a methodology to abstract RTL IPs into corresponding TL descriptions. The possibility of automating the methodology is deeply analyzed. In particular, the paper shows which abstraction levels can be reached without requiring human intervention, according to the characteristics of the design to be refined. A set of experimental results are finally reported to confirm the effectiveness of the methodology

The paper describes a high-level pseudodeterministic ATPG that explores the DUT state space by exploiting an easy-to-traverse extended FSM model. Testing of hard-to-detect faults is thus improved. Generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences generated by the proposed ATPG allows to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs.

Designers of factory automation applications increasingly demand tools for rapid prototyping of hardware extensions to existing systems and verification of resulting behaviors through hardware and software co-simulation. The paper presents a framework for the timing-accurate co-simulation of HDL models and their verification against hardware and software running on an actual embedded device of which only a minimal knowledge of the current design is required. Experiments on real-life applications show that early architectural and design decisions can be taken by measuring the expected performance on the models realized using the proposed framework.

The use of model checking to validate descriptions of digital systems lacks a coverage metrics. If the set of formal properties defined to prove the correctness of the design is incomplete, the verification can lead to a false sense of security. This paper refines, extends, and compares with other symbolic approaches, a methodology to estimate the incompleteness of formal properties, which exploits a high-level fault model and functional ATPG.

This paper presents an EFSM-based approach for functional automatic test pattern generation (ATPG). It shows how a particular kind of extended FSM (EFSM) can be efficiently traversed by a pseudo-determinist ATPG to control and propagate faults for a functional description of a design. Functional ATPG on such EFSM models have been showed to be more efficient than the ATPG on the original design. However, test sequences generated on such an EFSM can lose their efficacy when simulated on the original description, since they may show some timing discrepancies. To solve this problem, this paper propose a strategy that manipulates the EFSM model.

In this paper we present the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs, A compositional approach is proposed and two properties-based techniques are described and compared in terms of properties refinement effort and simulation speed delay.

Logical consequence between properties is generally examined by using theorem proving, which may require a large amount of time and space resources. This paper proposes a faster approach, which analyzes logical consequences by observing the property capability of revealing high-level faults. We consider a set of properties defined to check the correctness of a design (DUV) with respect to the specification. The paper proves that if there is only one property that distinguishes between a faulty and a fault-free behavior of the DUV, and then it cannot be a logical consequence of the remaining properties. It is shown that the reverse implication of such a theorem depends on the selected high-level fault model. According to these theoretical results, the paper proposes a method to analyze logical consequence of properties based on high-level fault simulation and theorem proving.

Mobile terminals are embedded systems with growing elaboration capacity, even still limited, which are continuously connected to a worldwide communication network. Thus, the idea of embedding in mobile terminals remote computing services seems attractive and it is more and more exploited. This paper evaluates a middleware platform based on the simple object access protocol (SOAP) to develop distributed applications on mobile terminals.

Recently a lot of multimedia applications have been emerging on portable appliances. They require both the flexibility of upgradeable devices (traditionally software based) and a powerful computing engine (typically hardware). In this context, programmable HW and dynamic reconfiguration allow novel approaches to the migration of algorithms from SW to HW. Thus, in the frame of the Symbad project, we propose an industrial design flow for reconfigurable SoC. The goal of Symbad consists of developing a system level design platform for hardware and software SoC systems including formal and semi formal verification techniques.

The paper deals with modelling and analysis of heterogeneous industrial networks architectures. At first homogeneous modelling strategy using the network simulator is presented and then the role of systemC and the use of the instruction set simulator is provided. Experimental results shows that the network cannot support the workload generated by the PLCs.

In a system-level design flow, the transition from a high-level description entry implies the refinement from an untimed, unpartitioned description to a real architecture where applications are executed on a programmable device and interact with ad-hoc hardware components. Simulation of such architectures requires the capability of efficient co-simulation of a model of hardware with a model of the processor. This paper presents two co-simulation methodologies, based on SystemC as hardware modeling language and on an instruction set simulator (ISS) as a model of the processor. The first one works at the SystemC kernel level and exploits potentialities of the GNU suite, whereas the second uses features offered by the operating system running on the ISS. The two methodologies improve co-simulation performance with respect to state-of the art methods, and provide different trade-offs between the simplicity of the programming model, the modeling power, and co-simulation performance.

Networked embedded systems pose several challenges in the modeling, simulation, and design domains. The presence of the network, in particular, makes an already critical task such as HW/SW co-simulation even more complex, since a three-way (HW/SW/network) co-simulation and co-design capability is required. Modeling of networks and their interaction with hardware and software is thus key for an effective design methodology at early stages of the design flow. In this work, we present a HW/SW/network co-simulation and co-design methodology, based on the integration of heterogeneous simulation environments such as systemC and NS (network simulator). This methodology has been successfully applied to the design of a system-on-chip performing the fast path of IPv4 routing, allowing to explore different HW/SW allocation for different network configurations.

More and more functional verification is attracting EDA researchers and industrial companies interested in digital system validation. Coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck at fault model? The paper presents an accurate analysis of the correlation between the high-level bit coverage fault model and the gate-level stuck-at fault model.

Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available. This paper proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs.

This work presents a modeling and analysis framework for heterogeneous industrial networks architectures, which is based on a tight integration of a network simulator with embedded software, middleware and a real-time operating system. This framework is suitable for modeling and simulating the behavior of typical components involved in factory automation applications (e.g., PLCs, remote controllers, operational screens, etc.) when they are connected through heterogeneous industrial networks. Experiments show that the framework allows to take early architectural decisions by evaluating the expected system performance based on the available models.

The design of state-of-the-art, complex embedded systems requires the capability of modeling and simulating the complex networked environment in which such systems operate. This implies the availability of both a networking modeling environment and traditional system-level modeling capabilities. In this paper we present a modeling and simulation methodology based on a timing accurate integration of a system-level modeling language (SystemC) and a network simulation environment (NS-2). The efficiency of the proposed design environment has been demonstrated on a description of a 802.11 MAC layer.

This paper describes a design methodology for the estimation of bus performance of a tuplespace for factory automation. The need of a tuplespace is motivated by the characteristics of typical embedded architectures for factory automation. We describe the features of a bus for embedded applications and the problem of estimating its performance, and present a rapid prototyping design methodology developed for a qualitative and quantitative estimation. The methodology is based on a mix of different modeling languages such as Java, C++, SystemC and Network Simulator2 (NS2). Its application allows the estimation of the expected performance of the bus under design in relation to the developed tuplespace.

This paper describes Laerte++, a high-level test pattern generator (TPG) for SystemC designs. All necessary features of a high-level TPG (e.g., fault models definition, hierarchical analysis, coverage measurements, etc.) are implemented by exploiting native SystemC characteristics funded on OO principles. The framework robustness and extensibility are guaranteed by an accurate use of software engineering methodologies for the Larte++ classes Definition and an extensive use of the Standard Template Library (STL) for data structure definition. Laerte++ allows to set up and run an ex-novo TPG session by adding very few C++ code lines to any SystemC design under test description. The applicability and the efficiency of the presented framework have been confirmed by the analyzed benchmarks.

A critical part of the design of HW/SW systems concerns the definition of the HW/SW interface. Such interfaces do not directly map a functionality of the system description, but they are inferred by the characteristics of the selected programmable device (CPUs, DSPs, ASIPs, etc.). Their addition to the design can modify the behavior of the original system, thus their verification is a hard task. The proposed verification methodology joins functional verification and property checking in order to avoid their respective limitations. The methodology is focused on SystemC descriptions that can be automatically synthesized. This is particularly important since commercial model checking tools work on structural hardware descriptions, which can be obtained by performing rapid prototyping of both HW and SW parts of SystemC models. The proposed approach has been verified on the SystemC model that is the reference synthesis example of one of the most powerful SystemC synthesis environment.

DfV exploits both functional verification and formal verification techniques; the former methods generate only approximated results, but they allow to rapidly identify errors and to avoid states explosion typical of formal techniques, whenever applied to complex designs in their entirety. On the contrary, formal techniques are necessary to identify corner-case errors and to reach a high level of confidence on the design correctness. All activities of the DfV flow should be integrated, as highlighted by arrows in Figure 1, in order to minimize the verification effort and to reuse verification products. Dotted lines in the figure show the cases when this integration and reuse is still under analysis and effective solutions must still be proposed. The majority of normal arrows show how integrated are already the verification activities. Manufacturing test starts when RTL and logic synthesis are completed and tries to identify relationships between features of the physical implementation and functions of the logic-level representation (tick box in the leftmost-bottom part of Figure 1). No effective methodologies have been proposed up to now to simplify manufacturing test activities by using results of the DfV methodology. This represents a waste of energies and it implies to solve again problems partially or totally solved during the verification phases. Main reasons of this separation are as follows: • Goals of verification and testing are different since internal monitors and checkers can be used in verification, while testing observe fault effects at the primary outputs. • Compositional verification examines one block at a time instead of the entire design, moreover, blocks are verified once, while they must be tested in any instance. • Verification testbenches provided with IP cores should be hierarchically composed to be used for testing. Disregarding these problems, some evidences there are among the usefulness of the confluence of manufacturing test and design validation: • Manufacturing faults can be effectively checked by addressing both functional errors and stuck-at faults. • Verification patterns can better address the problem of chip characterization than stuck-at oriented patterns. • Equivalence properties could be useful in faults diagnosis. • ATPGs can be moved from the gate level to the RT and system levels to generate functional test patterns and to help properties verification. Moreover, the following confluence opportunities are not exploited in the current testing tools, but they could be in a easy way: • Functional test patterns could be used to guide gatelevel ATPGs. • Verification environments and constraints could be used to guide gate-level ATPGs. • Properties could be used to guide the gate-level ATPGs (particularly in the case of sequential testing). This brief analysis has highlighted some directions for researches and implementations, which could further push the confluence of manufacturing test and design validation.

The use of model checking to validate descriptions of digital systems lacks a coverage metrics. The set of proven properties can be incomplete, thus not guaranteeing the behavioral checking completeness of the digital system implementation with respect to the specification. This paper proposes a coverage methodology based on a combination of model checking, high-level fault simulation and automatic test pattern generation, to estimate the incompleteness of a set of formal properties. The adopted high-level fault model allows to join dynamic and formal verification.

Verification of the functionality of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task because it is impossible to completely exercise the specification by exhaustively applying all input patterns. We present a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral error model. First, we generate a reduced number of functional test vectors for each process of the specification by using a new analysis metric which we call bit coverage. The error model based on this metric allows the identification of possible design errors represented by redundancies in the VHDL code. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when it is interconnected to other processes. If this is not the case, the analysis of the nonapplicable inputs provides identification of possible design errors due to erroneous interconnections. The bit-coverage provides complete statement, condition and branch coverage; and we experimentally show that it allows the identification of possible design errors. Identification and removal of design errors improves the global testability of a design.

Many approaches have been proposed for digital system verification, either based on simulation strategies or on formal verification techniques. Both of them show advantages and drawbacks and new mixed approaches have been presented in order to improve the verification process. Specifically, the adoption of formal methods still lacks a coverage metrics to let the verification engineer get a measure of which portion of the circuit is already covered by the written properties that far and which parts still need to be addressed. The present paper describes a new simulation based methodology aimed at measuring the error coverage achieved by temporal assertions proved by model checking. The approach has been applied to the description of a protocol converter block, and some preliminary results are presented in the paper.

Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct integration in a design implies more complex verification problems. IPs are usually provided with their own test patterns that can be used only by applying design for testability techniques onto the chip. Whenever physical faults must be detected, this approach is reasonable, even if it implies circuit performance degradation. However, it is completely useless at the design level, when the correct integration of the IPs into the global design must be investigated. At this level, proprietary test sequences must be generated in relation to the actual use of the IPs into the design. In this paper, the SystemC language is exploited to define a design verification framework for integration test of IP-cores. Intellectual properties of cores are guaranteed by adopting a client/server simulation architecture and by allowing functional test generationon faulty IP-core models without disclosing their internal structure. The methodology can be applied to mixed descriptions based on VHDL and SystemC, since an abstraction layer has been defined allowing clients and/or servers to be indifferently described in VHDL or SystemC. Finally, remote simulation can be also performed locally to avoid bandwidth bottleneck and the test generation process can be indifferently applied at lower abstraction levels such as RT and gate.

We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within the SystemC simulation framework. The integration is based on the well-known concept of bus wrapper, that realizes the interface between the ISS and the simulator. The proposed solution uses an ISS-wrapper interface based on the standard gdb remote debugging interface, and implements two alternative schemes that differ in the amount of communication they require. The two approaches provide different degrees of tradeoff between simulation granularity and speed, and show significant speedup with respect to a micro-architectural, full SystemC simulation of the system description.

In order to reduce the time-to-market and simplify gate-level test generation for digital integrated circuits, GA-based functional test generation techniques are proposed for behavioral and register transfer level designs. The functional tests generated can be used for design verification, and they can also be reused at lower levels (i.e. register transfer and logic gate levels) for testability analysis and development. Experimental results demonstrate the effectiveness of the method in reducing the overall test generation time and increasing the gate-level fault coverage.

Presents an analysis of the behavioral descriptions of embedded systems to generate behavioral test patterns that are used to perform the exploration of design alternatives based on testability. In this way, during the hardware/software partitioning of the embedded system, testability aspects can be considered. This paper presents an innovative error model for algorithmic (behavioral) descriptions, which allows for the generation of behavioral test patterns. They are converted into gate-level test sequences by using more-or-less accurate procedures based on scheduling information or both scheduling and allocation information. The paper shows, experimentally, that such converted gate-level test sequences provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given behavioral specification. For this reason, our behavioral test patterns can be used to explore testability alternatives, by simply performing fault simulation at the gate level with the same set of patterns, without regenerating them for each circuit. Furthermore, whenever gate-level ATPGs are applied on the synthesized gate-level circuits, they obtain lower fault coverage with respect to our behavioral test patterns, in particular when considering circuits with hard-to-detect faults.

Functional testing of HDL specifications is one of the most promising approaches for the verification of the functionalities of a design before synthesis. The contribution of this work is the development of a test generation algorithm targeting a new coverage metric (called bit-coverage) that provides full statement coverage, branch coverage, condition coverage and partial path coverage for behaviorally sequential models. The behavioral test sequences can be also the only way to evaluate testability of VHDL model for which a gate-level representation is not available (e.g third-party cores), since the behavioral error model is characterized also by a high correlation with the RT and gate-level stuck-at fault model. Moreover the preciseness of the proposed coverage metric makes the identified test sequences more effective in identifying design errors, than other test patterns developed by following standard coverage metrics.

More and more people are starting to use the SystemC description language to model and simulate new designs. This is due mainly to the simplicity and power of the language. The number of models written in SystemC currently available is still very limited and testing SystemC descriptions is still an open issue, since the language is new and researchers are looking for efficient error models and coverage metrics. This paper presents AMLETO, a multi-language environment developed to efficiently test embedded systems and IP-Cores. Using IIR, an HDL language independent representation, it supplies: fast translation from VHDL to SystemC of design descriptions and viceversa, generation and setup of customized TPGs for the design under test and generation of erroneous models capable of simulating the presence of design errors.

An effective selection of the more suited IP-core, available for a particular design, should be based on some simulation sessions. However, simulation models cannot be close enough to the real models of the core to protect the intellectual property. This paper proposes a Web-CAD methodology for IP-core analysis based on a client/server simulation architecture. The core vendor can make available to the public even the core models used for core synthesis without disclosing IP information. On the other side, the core user can simulate the remote core in the local simulation environment in the same way a local library component is simulated. To achieve this result, some problems concerning the non equivalence of the event driven semantic and the message driven semantic have been analyzed and solved.

This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. All components of the simulation environment are automatically built starting from the VHDL specification of the description under test. The effectiveness of the simulator has been measured by using a random functional test generator. Functional test patterns produce, on some benchmarks, a higher gate-level fault coverage than the fault coverage achieved by a very efficient gate-level test pattern generator. Moreover, functional test generation requires a fraction of the time necessary to generate test at the gate level. This is due to the possibility of effectively exploring the test patterns space since error simulation is directly performed at the VHDL level.

This paper describes a functional level rest pattern generator, which combines two techniques: genetic algorithms (GAs) and binary decision diagrams (BDDs). The combined execution of such two techniques achieves better results for functional testing, than the single application of each separated technique. The entire set of functional errors is examined in a shorter time and a more compact test set is produced. The reason of this interesting result has been analyzed in the paper. It mainly depends on the fact that hard to detect errors for GA-based testing techniques are easy to detect than errors for BDD-based techniques and vice versa. The two testing approaches are thus complementary and can effectively cooperate.

The aim of this paper is to show the effectiveness of a high-level approach to testability analysis and test pattern generation, when analyzing different classes of architectures implementing the same specification. A unique test set is derived on the behavioral specification, based on a functional error model, which shows a high correlation with the single stuck-at-gate-level fault model. Such a test set is then tailored to the particular gate-level implementation by transforming it into a specific test sequence, based on the scheduling adopted by the high-level synthesis. Experimental results show that the application of such test sequences allows one to accurately evaluate the testability of the architecture in terms of gate-level fault coverage, in a fraction of the time required by a gate-level test pattern generator.

A testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generators.

This paper presents a binary decision diagram (BDD)-based algorithm for the optimization of the driven machine, M/sub 2/, of a finite-state machine (FSM) network with cascade connection, M/sub 1//spl rarr/M/sub 2/. The technique we propose relies on redundant faults identification and removal. A fault, f, located into machine M/sub 2/, is redundant with respect to the overall network if the driving machine M/sub 1/ is not able to generate any test sequence for such a fault. When the state transition graph (STG) specifications of the network components are available, the standard way for checking the redundancy condition for the considered fault requires one to first construct the product machine M/sub 2//spl times/M/sub 2//sup F/, where M/sub 2//sup F/ is the faulty FSM, then to connect it to the driving machine, and finally to perform reachability analysis on the composed machine M/sub 1//spl rarr/M/sub 2//spl times/M/sub 2//sup F/. Clearly, the size of such machine limits the applicability of the approach above to systems whose components have a few tens of states at most, even when symbolic traversal algorithms are used. Since we are interested in dealing with networks of larger FSM's (i.e., machines whose STGs can not be represented explicitly), we propose to use the product automaton P'=A/sub 1//spl times/A/sub f/, where A/sub 1/' is the finite automaton (FA) accepting all the output sequences of M/sub 1/, and A/sub f/ is the FA accepting all the test sequences for fault f, instead of machine M/sub 1//spl rarr/M/sub 2//spl times/M/sub 2//sup F/. This simplifies sensibly the task of the reachability analysis program, since A/sub f/ has considerably less states and less edges than the product machine M/sub 2//spl times/M/sub 2//sup F/ and, thus, the size of the BDD representation of its transition relation is much more easily manageable. In addition, differently from other approaches, automaton A/sub 1/' is not required to be deterministic and state minimal. This allows us to avoid the application of determinization and state minimization procedures whose complexity is exponential. We present experimental results For examples (i.e., network of interacting controllers) on which existing optimization methods are not applicable, due to the size of the component FSM's. We also provide a comparison to the data produced by state-of-the-art FSM network optimizers on small benchmarks in order to show the effectiveness of our approach.

Verification of the functional correctness of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task since it is impossible to completely exercise the specification by exhaustively applying all input patterns. The paper aims at presenting a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral fault model. First, we generate a reduced number of functional test vectors for each process of the specification which allows complete code statement coverage and bit coverage, allowing the identification of possible redundancies in the VHDL process. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when interconnected to other processes. If this is not the case, the analysis of the nonapplicable inputs provides identification of possible code redundancies and design errors. Experimental results show that bit coverage provides complete statement coverage and a more detailed identification of possible design errors.

This paper presents a testable synthesis methodology applicable to any top-down design method based on hardware-description-language descriptions, or graphical representations. The methodology is targeted on control-dominated applications and it is based on the identification and removal of a new class of redundant faults, called functionally redundant faults. The formal relation between functionally redundant faults and sequentially redundant faults is introduced. Moreover, the relation between functionally redundant faults and logic synthesis algorithms based on local don't cares is shown. Functionally redundant faults are identified and removed by comparing the implemented synchronous sequential circuit, which can be technology dependent, to its specification. The specification can be a single finite state machine (FSM), a set of interacting FSMs, or a hierarchical FSM that allows the description of highly complex controllers. The proposed methodology produces testable circuits, with area reduction, still mapped on the same technology library, and it manages circuits which cannot be handled by other methods presented in the literature.

This paper presents a methodology for power estimation of designs described at the behavioral-level as the interconnection of functional modules. The input/output behavior of each module is implicitly stored using BDDs, and the power consumed by the network is estimated using a novel and accurate entropy-based approach. As a demonstration example, we have used the proposed power estimation technique to evaluate and compare the effects of some architectural transformations applied to a reference design specification on the power dissipation of the corresponding implementations.

No abstract available.

Testability analysis of VHDL sequential models is the main topic of this paper. We investigate the possibility to obtain information about the testability of a sequential VHDL description before its actual synthesis. The analysis is based on an implicit fault model that injects faults into a BDD based description extracted from the VHDL representation. Such an injection is related to the original VHDL representation thus allowing the identification of potential testability problems before RTL and logic synthesis. Fault injection is performed efficiently by exploiting the concept of fault clustering, that is the possibility of grouping faults and analyzing them concurrently. The proposed methodology is applied to benchmarks for efficiency evaluation and to a real VHDL description.

A methodology for modifying VHDL descriptions is the core of this paper. Modifications are performed on general RTL descriptions composed of a mix of control and computation, that is, the typical type of description used for designing at the RT level. Such VHDL descriptions are automatically partitioned into a reference model composed of a controller driving a data-path. We call this transformation "VHDL restructuring". A set of restructuring steps is presented aiming at partitioning any VHDL description while guaranteeing the semantic equivalence of the restructured description with the original one. The main motivation to restructuring is the identification and separation of the two parts (FSM+data-path) which can thus be analyzed by using "ad hoc" synthesis, testability and design for testability algorithms. Promising results show that restructuring can sensibly impact on synthesis and testability.

This paper proposes a behavioral-level test pattern generation algorithm for behavioral VHDL descriptions. The proposed approach is based on the comparison between the implicit description of the fault-free behavior and the faulty behavior, obtained through a new behavioral fault model. The paper will experimentally show that the test patterns generated at the behavioral level provide a very high stuck-at fault coverage when applied to different gate-level implementations of the given VHDL behavioral specification. Gate-level ATPGs applied on these same circuits obtain lower fault coverage, in particular when considering circuits with hard to detect faults.

Testability analysis and test pattern generation for neural architectures can be performed at a very high abstraction level on the computational paradigm. In this paper, we consider the case of Hopfield's networks, as the simplest example of networks with feedback loops. A behavioral error model based on finite-state machines (FSM's) is introduced. Conditions for controllability, observability and global testability are derived to verify errors excitation and propagation to outputs. The proposed behavioral test pattern generator creates the minimum length test sequence for any digital implementation.

This paper proposes a methodology, implemented in a tool, to automatically generate the main classes of error control codes (ECC's) widely applied in computer memory systems to increase reliability and data integrity. New code construction techniques extending the features of previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes have been integrated in the tool. The proposed techniques construct systematic odd-weight-column SEC-DED-SBD codes with odd-bit-per-byte error correcting (OBC) capabilities to enhance reliability in high speed memory systems organized as multiple-bit-per-chip or card.

By considering test costs at the behavioral level, test problems can be pointed out during the first phases of the design flow. Thus, in case either some testability problems are identified or the size (and hence the cost) of the test set results to be too high, the designer or the high level synthesis tool can modify the circuit to reduce such testability problems. The main problem is the correspondence between the behavioral and RT or gate level fault models. To overcome such limitation, the paper presents a design flow based on the behavioral fault model modification ("evolution") depending on the actual RTL implementation.

Control-dominated architectures are efficiently described by means of graphical representations based on statecharts. Statecharts descriptions can be automatically translated into HDL representations (VHDL or Verilog) which are directly synthesized into gate-level netlists. This paper describes a set of rules which transform, if possible, a statecharts description into a simpler representation based on hierarchically interconnected FSMs (HFSM). The comparison of the HFSM description with the gate-level synthesized net-list allows to efficiently perform redundancies removal and test pattern generation. Thus, by applying the proposed testing strategy, fully testable implementations can be obtained even for such devices which cannot be satisfactorily analyzed at the gate level only.

The test problem increasingly affects the system design process and related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. The paper presents a global toolset architecture for testability analysis and test pattern generation. Three abstraction levels are considered in this design flow, from the behavioral specifications, through RTL descriptions, down to gate level. In all these phases, VHDL is chosen as the referring description language. The paper then presents an application scenario, detailing the results achieved by the proposed methodology.

This paper presents an implicit methodology that constrains a test pattern generator to identify test sequences which can be reproduced by cellular automata (CA). The so identified CA can be synthesized as an autonomous finite state machine and can be attached to the inputs of a circuit under test (e.g., a controller). In this way, the circuit under test preserves its integrity and its performance is not affected by the proposed testing technique. The overall device (controller+CA) is an off-line self-testable circuit which con potentially self-test all stuck-at faults both of the controller and the CA. Thus, the method can be viewed as a BIST strategy based on the embedding of deterministic test sequences.

Control-dominated architectures are usually described in a hardware description language (HDL) by means of interacting FSMs. A VHDL or Verilog specification can be translated into an interacting FSM (IFSM) representation as described here. The IFSM model allows us to approach the testable synthesis problem at the level of each FSM. The functionality is modified by the addition of transparency to data flow. The complete testability of the IFSM implementation is thus achieved by connecting fully testable implementations of each modified FSM. In this way, test sequences separately generated for each FSM are directly applied to the IFSM to achieve complete fault coverage. The addition of test functionality to each FSM description, and its simultaneous synthesis with the FSM functionality, produces a lower area overhead than that necessary for the application of a partial-scan technique. Moreover, the test generation problem is highly simplified since it is reduced to the test generation for each separate FSM.

This paper presents a novel optimization algorithm for FSM networks that relies on sequential test generation and redundancy removal. The implementation of the proposed approach, which is based on the exploitation of input don't care sequences through regular language intersection, is fully symbolic. Experimental results, obtained on a large set of standard benchmarks, improve over the ones of state-of-the-art methods.

This paper presents a new testing strategy for networks of interacting FSMs. The approach allows us to generate test patterns for faults in the network by separately handling the network's components. The proposed algorithms are fully symbolic; therefore, they allow the manipulation of large designs. Experimental results, though preliminary, are promising.

Test pattern storage is an important problem affecting all Design for Testability (DfT) techniques based on scan-path. Test compaction is the key idea to reduce this problem, but in case of partial-scan test compaction would concern the concatenation and overlapping of test sequences instead of test vectors. Unfortunately, standard sequential TPGs do not show sufficient capabilities in test sequences compaction. Thus, the paper presents an innovative compaction strategy for test sequences based on implicit techniques. Preliminary results show that the use of the presented technique can sensibly reduce the amount of test patterns which mast be stored and applied.

Specification of large complexity controllers in industrial design environments is performed by means of a top-down methodology leading to a description based on a hierarchy of FSMs. This paper presents a set of algorithms which compare such hierarchical descriptions with their structural implementations to produce irredundant circuits for which test patterns are easily derived. These algorithms can be inserted into any commercial design flow, based on VHDL descriptions, thus creating a synthesis for testability environment which provides testable and optimized gate-level descriptions.

Testing of array architectures is an important issue because of the relevance that these structures are assuming in VLSI/WSI designs. The DfT techniques presented in this paper represent a possible approach to allow the verification of the cells composing the entire structure. The structural methodologies cope with the accessibility problems by modifying the interconnection network to "isolate" the cell in exam from the others; the functional approach modifies the cell making it transparent with respect to the data flow if the cell is not being tested. Both techniques aim at defining a sequential array architecture whose elements can be tested by applying patterns defined for the single cell and achieving the same coverage notwithstanding the embedding constituted by the array interconnections.>

This paper introduces and evaluates functional fault models for test pattern generation of sequential circuits at the finite state machine level. Evaluation of the proposed fault models against their gate level fault coverage on multi-level implementations is presented. The relationships between functional and gate level fault coverage are discussed.>