Advanced packaging technologies are reshaping; semiconductor integration, offering unprecedented improvements in performance, efficiency, and miniaturization. Among these Fan-Out Wafer-Level Packaging (FOWLP) has emerged as a transformative solution, pushing the limits of chiplet integration through its superior electrical performance, reduced footprint, and enhanced thermal management However, FOWLP presents several challenges, including coefficient of thermal expansion mismatch, warpage, die shift, and post-molding protrusion, all of which can lead to misalignment and defects. Moreover, thermo-mechanical stresses in the organic package induce warpage and delamination, further exacerbating weak defects during runtime operation. To address these challenges, we propose a comprehensive defect analysis and testing framework for FOWLP interconnects. Defects are mapped to equivalent electrical circuit models, allowing for precise fault characterization. A built-in self-test (BIST) architecture is introduced to detect open and bridging faults while accurately diagnosing fault types and localizing them. An embedded ring oscillator within the BIST network detects weak opens, bridging and coupling faults, quantifying the size of the defects. We demonstrate how this test framework can be utilized at different supply voltage corners and for various transistor sizes to reduce fault-effect aliasing due to process variations, thereby ensuring robust diagnostics, yield learning, and silicon lifecycle management. The effectiveness of the ring oscillator circuit is validated through HSPICE simulations using equivalent faulty circuit models for a 7 nm CMOS technology.

The exponential growth in test data volume for modern Systems-on-Chip (SoCs), combined with a decreasing number of available test pins, has led to increased test time and complexity. Simultaneously, the industry’s drive for higher quality and lower Defective Parts Per Million (DPPM) necessitates continuous monitoring, testing, and repair Silicon Lifecycle Management (SLM). The advent of multi-die packaging technologies, such as 2.5D and 3D stacked integration, further exacerbates these challenges by introducing additional layers of interconnect and access constraints.Universal Chiplet Interconnect Express (UCIe) emerges as a compelling solution for delivering test content to all constituent dies at-speed, post-packaging. UCIe enables seamless test access across various lifecycle stages, including wafer sort, package test, System Level Test (SLT), and In-System Test (IST).This paper introduces a silicon-proven methodology that integrates the UCIe protocol with advanced SLM techniques to address the critical challenges of access, test, measurement and repair in complex multi-die SoC designs. Silicon results from test vehicles fabricated on TSMC N3P process with CoWoS-S packaging demonstrate complete interconnect, logic, and memory test, repair, and monitoring capabilities, validating the effectiveness and scalability of the proposed approach for next- - generation multi-die systems.

Rapid yield ramp-up and precise defect identification are crucial in advanced semiconductor development, especially as technologies reach 5nm and below. Scan-based testing, the primary Design for Testability (DFT) method, is essential, but scan chains are susceptible to defects, hindering yield learning. Traditional fault isolation, like Laser Voltage Probing, is ineffective in more advanced processes due to backside power rail constraints. Hardware solutions impact power, performance, and area (PPA), while software lacks accuracy. This paper introduces two methods to improve scan chain diagnosis: a multi-mode scan design with soft repair capability and a hybrid hardware-software approach. The multi-mode design identifies defective scan cells, aiding logic yield learning before Physical Failure Analysis (PFA), achieving a 100% predicted PFA success rate. The hybrid scalable method uses hardware for coarse diagnosis with minimal PPA impact and software for detailed analysis, leveraging existing test patterns. These approaches enhance scan chain diagnosis, supporting faster yield ramp-up and defect identification.

System-on-Wafer (SoW) technology integrates multiple chiplets onto a single wafer substrate, offering enhanced performance for high-computation applications. This paper presents an innovative 3D test access architecture designed for complex SoW systems. The proposed omnidirectional test access architecture, compliant with IEEE Std. 1838, provides a scalable, plug-and-play testing solution for comprehensive multi-directional testing. It enables efficient scan path configuration, optimizing test scheduling while reducing power consumption and minimizing timing-related impacts. A case study involving a SoW system with four chiplets arranged in a 2x2 configuration validates the architecture's feasibility and effectiveness, demonstrating its potential to enhance SoW testability and reliability.

Scan design adversely affects design performance, including speed, power, and routing congestion. Scan partitioning and reordering are required to mitigate these effects. We present an unsupervised machine learning-based method for scan partitioning to reduce the total scan wire length and make scan chains as compact as possible. For scan partitioning, we use the K-Means clustering method and reorder flops in a scan chain using the Traveling Salesman Problem (TSP) algorithm. Experimental results for three CPU designs show that significant savings in real wire length (2-3%), as well as a reduction in timing impact (27%), can be achieved with the proposed method compared to the best case obtained by a commercial EDA flow. Additionally, the optimized scan stitching also helped improve Design Rule check (DRC) violations, which aids in design closure.

A multi-die 3DIC is constructed by integrating multiple dies into a stack. These dies are interconnected via die-to-die (D2D) interconnects facilitated by I/O pads, which manage signal load and provide electrical protection to both the die and the overall system. The number of D2D interconnects is anticipated to increase significantly, rising from a few thousand today to several hundred thousand in the coming years. Consequently, ensuring the functionality and performance of 3DIC systems requires rigorous testing of not only the die logic but also the pads and interconnects at both the die and stack levels. In this paper, we explore the Design for Test (DFT) and testing challenges involved in handling various types of pads, ranging from simple to complex custom designs, within a multi-die 3DIC system. We also examine the tools and methodologies provided by Electronic Design Automation (EDA) tools to support these challenges, specifically focusing on implementations compliant with the IEEE 1838 standard.

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

Chip-Iet based multi-die 3DIC design methodology is the paradigm shift in semiconductor manufacturing that enables scalable design integration for SysMoore era. Stacking multiple heterogeneous dies in a single stack opens chip design to a world of unexplored challenges. One such challenge is testing of the individual dies and the integrated complex stack to improve DPM. The IEEE 1838 standard defines 3DIC DFT architectures for individual dies and stack level test. In this paper we present a case study on an industrial design to leverage EDA tools and flows to implement IEEE 1838 compliant DFT architectures for full die and integrated stack.

3D ICs have increasingly become popular as they provide a way to pack more functionality on a chip and reduce manufacturing cost. TSMC offers a number of packaging technologies under the umbrella of "3D Fabric" to suit different product requirements. Just like any new technology, 3D Fabric brings forward several challenges associated with system, design, thermal as well as testing that require effective and efficient solutions before 3D Fabric can be used in high volume production. In this presentation, we will give a brief introduction about various 3D Fabric offerings and discuss challenges from a semiconductor foundry perspective. Next, we present an overview of solutions along with what EDA needs to solve. Lastly, how various IEEE Standards such as 1838, and 1149.1 can help in streamlining and standardizing testing approaches for 3D Fabrics will be discussed.

Author: Sandeep Kumar Goel

Chip designers typically do not consider design-for-diagnosis (DfD) for manufacturing defects while implementing an integrated circuit and its design-for-test features. The lack of emphasis on DfD results in low diagnosis resolution and limited physical failure analysis (PFA) success rate when diagnosis is carried out using advanced techniques. To the best of our knowledge, no practical solution is available today to analyze the diagnosability of a design and improve it before tapeout. Furthermore, techniques that are specific to a given design cannot be reused for other chips. Therefore, we first propose a general structure-based diagnosability scoring model that can be used to analyze the diagnostic resolution for any chip. After the diagnosability analysis, we consider inserting additional observation points (OPs) for diagnosability enhancement. Given a constraint on the maximum number of inserted OPs, we propose a three-stage OP insertion (OPI) method, which includes: (i) selection of hard-to-diagnose (HTD) faults; (ii) mixed location ranking based on a structure-based diagnosability “repair” scoring model; (iii) information update and final location selection for a better diagnosability “repair” effect. The use of OPI results in higher fault “repair” rates and significant improvement in diagnosability. Experiments on benchmark circuits and industrial designs demonstrate the effectiveness of the proposed DfD solution.

System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC'02 SOC Test Benchmarks show 3.5 and 20 percent reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test scheduling.

Through-silicon vias (TSVs) provide high-density vertical interconnects between dies and enable the creation of 3-D ICs having higher performance and lower power consumption than traditional 2-D ICs. A practical TSV-based 3-D integration approach is to place multiple dies (or die stacks) side by side on a passive silicon interposer base, in which there are TSVs and metal wires serving as interconnects. In this paper, we propose a post-bond design-for-test architecture and a test strategy for such interposer-based 3-D ICs. Functional package pins and interconnects are reused to build multibit parallel test access mechanisms (PTAMs), which provide post-bond test access with no or low extra area costs. Four PTAM architectures are presented, and the corresponding PTAM optimization algorithms are proposed which can quickly identify the best PTAM configuration to achieve the shortest test time. We also propose an algorithm for adding dedicated test interconnects to improve test bandwidth at the expense of extra microbumps and metal wires. Experimental results show that the proposed techniques are effective in test length (and therefore test time) reduction. Moreover, cost–benefit analysis results suggest that our approaches have lower total test costs compared with a base-case one-bit JTAG-only solution.

Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.

For decades, EDA test generation tools for digital logic have relied on the Stuck-At fault model, despite the fact that process technologies moved forward from TTL (for which the Stuck-At fault model was originally developed) to nanometer-scale CMOS. Under pressure from their customers, especially in quality-sensitive application domains such as automotive, in recent years EDA tools have made great progress in improving their detection capabilities for new defects in advanced process technologies. For this Hot-Topic Session, we invited the three major EDA vendors to present their recent greatest innovations in hiqh-quality automatic test pattern generation, as well as their lead customers to testify of actual production results.

Recent advances in semiconductor process technology especially interconnects using Through-Silicon Vias (TSVs) enable heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and then stacked together to form a system. Compared to conventional wire-bond chip interconnections, TSVs offer several advantages such as high density, low latency, low power, and possibly lower cost. TSVs provide vertical interconnects and hence naturally used for 3D vertical stacking of multiple dies, However, TSVs also have attractive benefits in interconnecting dies, which are placed next to each other on top of a passive silicon interposer.

Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.

2.5D Stacked ICs (2.5D-SICs) consist of multiple active dies (or 3D towers of active dies), which are placed side-by-side on top of and interconnected through a passive silicon interposer base which contains Through-Silicon Vias (TSVs). A previously presented post-bond test and Design-for-Test(DfT) strategy for such 2.5D-SICs implements a serial Test Access Mechanism (TAM) for interposer and micro-bump testing. In addition, it tries to identify an as-wide-as-possible set of functional interposer interconnects that can be reused as parallel TAMs to the various dies. In this paper, we extend that approach with the concept of Multi-Visit TAMs, i.e., parallel TAMs which are allowed to visit the same die more than once. For minimal additional hardware costs, the Multi-Visit TAMs succeed significantly more often in identifying a valid parallel TAM and achieve significantly lower test lengths.

Using Through-Silicon Vias (TSVs) in three-dimensional stacked ICs (3D-SICs) has benefits in terms of interconnect density, performance, and power dissipation. For 3D-SICs, an extension of the Design-for-Test architecture based on die-level wrappers is required to enable pre-bond die testing as well as modular post-bond die and interconnect testing. This paper presents an approach that automates the insertion of die wrappers. Experimental results show that the user can perform automated 3D-DfT insertion through existing EDA tools with negligible area costs, and verify the proposed DfT by test pattern generation and simulation.

Three-dimensional stacked ICs (3D-SICs) based on Through-Silicon Vias (TSVs) provide attractive benefits such as smaller form factor, higher performance, and lower power. So far, prior work on Design-for-Testability (DfT) only focused on 3D-SICs consisting of a single "tower", i.e., a 3D-SIC in which each stack level contains exactly one die. 3D stacking technology allows to place multiple dies on top of a common base die, resulting in 3D-SICs with multiple "towers". This paper presents a generic DfT architecture for 3D-SICs having any number of "towers", possibly including "sub-towers". We also present efficient test control mechanisms. Experimental results show that the proposed architecture has a negligible area cost for medium-sized and larger industrial designs, and therefore provides a cost-effective test solution for 3D-SICs.

Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects for system chips that consist of multiple dies. In “2.5D” Stacked ICs (2.5D-SICs), multiple dies without TSVs are stacked side-by-side on top of a passive silicon interposer base containing TSVs. In true 3D-SICs, multiple dies containing TSVs themselves are vertically stacked; one or multiple of such stacks are possibly placed on a passive silicon interposer. This paper proposes a post-bond test and design-for-test (DfT) strategy for 2.5D- and 3D-SICs containing a passive silicon interposer base. Functional interconnects in the interposer are reused as much as possible in order to keep the interposer cost low.

Through-silicon via (TSV)-based 3-D stacked ICs (SICs) are becoming increasingly important in the semiconductor industry. In this paper, we address test architecture optimization for 3-D stacked ICs implemented using TSVs. We consider two cases, namely 3-D SICs with die-level test architectures that are either fixed or still need to be designed. We next present mathematical programming techniques to derive optimal solutions for the architecture optimization problem for both cases. Experimental results for three handcrafted 3-D SICs comprising of various systems-on-a-chip (SoCs) from the ITC'02 SoC test benchmarks show that compared to the baseline method of sequentially testing all dies, the proposed solutions can achieve significant reduction in test length. This is achieved through optimal test schedules enabled by the test architecture. We also show that increasing the number of test pins typically provides a greater reduction in test length compared to an increase in the number of test TSVs. Furthermore, we show that shorter test lengths are generally achieved with the larger, more complex dies lower in the stack. This is because test data must pass through every die lower in a stack in order to reach its target die, and with the larger dies lower in the stack, more test bandwidth may be provided to these dies using fewer routing resources.

For sub-nanometer designs, testing for small-delay defects (SDDs) is essential to achieve low defect escapes for the manufactured silicon. Existing solutions for testing SDDs are not practical for high-volume production environments due to large pattern count or long compute time, or both. In this paper, we present a production-friendly method that takes the circuit topology into account while generating patterns for SDDs. Experimental results on several IWLS'05 benchmark and six industrial circuits show that compared to the default timing-aware pattern set, the proposed method reduces pattern count an average of 172% for IWLS benchmarks and an average of 105% for industrial circuits. We demonstrate the production-worthiness of our approach by using several quality metrics and showing that the proposed method provides similar or higher coverage for SDDs compared to the default timing-aware ATPG, but only with a significantly small number of test patterns and in significantly small run time.

Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D stacked ICs implemented using Through-Silicon Vias (TSVs) technology. We consider 3D-SICs with both fixed given and yet-to-be-designed test architectures on each die and show that both corresponding problem variants are NP-hard. We next present mathematical programming techniques to derive optimal solutions for these problems. Experimental results for three handcrafted 3D-SICs of various SOCs from the ITC'02 SOC test benchmarks show that compared to the baseline method of sequentially testing all dies in a stack, the proposed solutions can achieve up to a 57% reduction in test time. We also show that increasing the number of test pins provides a greater reduction in test time compared to an increase in the number of TSVs. Furthermore, it is shown that 3D stacks with large and complex dies at lower layers require less test time than stacks with complex dies at higher layers.

Small delay defect (SDD) testing is expected to become more prevalent as technology nodes continue to shrink and design frequencies continue to increase. In this paper, we critically examine previously published methods for evaluating SDD coverage and identify their shortcomings as an accurate and practical coverage metric. We propose an accurate method for measuring the coverage of small delay defects by any given pattern set. We demonstrate that the proposed metric overcomes the identified shortcomings of previously published approaches. For several ISCAS and industrial circuits, we generate test patterns and compare their SDD coverage values using different methods. Experimental results also demonstrate that the proposed method is several times faster to compute. Finally, we evaluate different testing strategies for screening small delay defects.

Shrinking feature size and increased wire density increase the likelihood of occurrence of bridge related defects. N- detect based pattern sets are used commonly to improve the detection of bridge defects. However, achieving high bridge coverage requires deterministic bridge sites extraction from physical layout and bridge fault pattern generation. In this paper, we present a comprehensive comparative analysis about the effectiveness of deterministic bridge fault patterns and n-detect patterns for two large designs (90 and 65 nm). We show that extracting different types of bridge faults is required as they represent different unique defect sites. Simulation results show that n-detect patterns have very poor bridge coverage performance and commonly used metric bridge coverage estimate (BCE) does not relate to the true bridge fault coverage. Finally, we discuss the DPPM impact for deterministic bridge fault and n-detect stuck-at patterns for the 90 nm design.

Testing for small delay defects is critical to guarantee that the manufactured silicon is timing-related defect free and to reduce quality loss associated with delay defects. Commercial solutions available for testing of small delay defects result in very high pattern count and run time. In this paper, we present two effective approaches for generating timing-aware transition fault patterns that target small delay defects. We identify a subset of transition faults that should be targeted by the timing-aware ATPG; while for the rest of the faults, classic non-timing-aware transition fault patterns can be generated. Experimental results for several industrial benchmarks show that the proposed approaches result in up to 75% reduction in test pattern count compared to existing timing-aware ATPG approaches.

Volume diagnostics introduces important means for yield learning as conventional techniques become more expensive and insufficient in identifying systematic yield limiters. Integrating DFM practices within the design flows requires faster identification and ranking of systematic yield limiters in the design. This paper presents a paradigm for identifying outliers in the fail signatures obtained from volume fail data using fail rate prediction from chip-level CAA analysis. Results from case study shows that a comparative analysis between predicted and observed fail rates can highlight potential yield limiters.

Many system-on-chip (SOC) integrated circuits today contain hierarchical (parent) cores that have multiple levels of design hierarchy involving "child cores". Hierarchy imposes a number of constraints on the manner in which tests must be applied to parent cores and their child cores. However, most prior work on wrapper design, test access mechanism (TAM) optimization, and test scheduling are hierarchy-oblivious, i.e., these techniques treat all cores in an SOC at the same level of hierarchy. We first show that wrappers, TAMs and test schedules designed for non-hierarchical SOCs are not valid for SOCs with hierarchical cores. We next present two approaches for the efficient testing of SOC with hierarchical cores. In the first approach, an existing wrapper design is modified such that that all constraints imposed by the hierarchy are satisfied and full flexibility is provided for TAM optimization and test scheduling. The second approach is based on a hierarchy-aware wrapper architecture for parent cores that operates in two disjoint modes for the testing of parent and child cores. We show how an existing test-architecture design algorithm can be adapted for use with these two methods. Results for the ITC'02 SOC Test Benchmarks show that the first approach offers lower test application times while the second approach requires less area overhead.

This paper shows that accurate fault detection and diagnosis are possible when applying a parity tree for space compaction of test responses and continuously observing the parity-tree output. We exploit that each set of faults results in a unique parity-tree output sequence that can be used as a unique fault signature for truly accurate fault detection and diagnosis. Our theoretical analysis shows that probabilities for fault cancellation and fault aliasing are extremely low and decrease with circuit size. Experimental results show that for a typical scan chain architecture in large industrial circuits, fault coverage is not affected by parity-tree space compaction for up to 256 scan chains, while diagnostic resolution is reduced by only 1% to 2%.

Multiple levels of design hierarchy are common in current-generation system-on-chip (SOC) integrated circuits. However, most prior work on test access mechanism (TAM) optimization and test scheduling is based on a flattened design hierarchy. We investigate hierarchy-aware test infrastructure design, wherein wrapper/TAM optimization and test scheduling are carried out for hierarchical SOCs for two practical design scenarios. In the first scenario, the wrapper and TAM implementation for the embedded child cores in hierarchical (parent) cores are delivered in a hard form by the core provider. In the second scenario, the wrapper and TAM architecture of the child cores embedded in the parent cores are implemented by the system integrator. Experimental results are presented for the ITC'02 SOC test benchmarks

The use of power switches in modern system chips (SOCs) is inevitable as they allow for efficient on-chip static power management. Leakage is today one of the main hurdles in low-power applications. Power switches enable power gating functionality, i.e., one or more parts of the SOC can be powered-off during standby mode leading in this way to savings in the overall SOCs power consumption. In this paper, we present a circuit and a method to test power switches. The proposed method allows testing of on/off functionality. In case of segmented power switches individual failing segments can be identified as well by using the proposed test strategy. The method requires only a small number of test patterns that are easy to generate. Furthermore, the proposed method is very scalable with the number of power switches and has a very small area-overhead.

Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and consider parameters like test time, index time, abort-on-fail, and contact yield. Conventional multi-site testing requires sufficient ATE resources, such as ATE channels, to allow the test of multiple SOCs in parallel. In this paper, we design and optimize on-chip DfT in order to maximize the test throughput for a given SOC and ATE. The onchip DfT consists of an E-RPCT wrapper, and, for modular SOCs, module wrappers and TAMs. We present experimental results for a Philips SOC and several ITC'02 SOC test benchmarks.

Complex SOCs are increasingly tested in a modular fashion, which enables us to record the yield-per-module. In this paper, we consider the yield-per-module as the pass probability of the module's manufacturing test. We use it to exploit the abort-on-fail feature of ATEs, in order to reduce the expected test application time. We present a model for expected test application time, which obtains increasing accuracy due to decreasing granularity of the abortable test unit. For a given SOC, with a modular test architecture consisting of wrappers and disjunct TAMs, and for given pass probabilities per module test, we schedule the tests on each TAM such that the expected test application time is minimized. We describe two heuristic scheduling approaches, one without and one with preemption. Experimental results for the ITC'02 SOC test benchmarks demonstrate the effectiveness of our approach, as we achieve up to 97% reduction of the expected test application time, without any modification of the SOC or ATE.

Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpoint modules during the design stage of the chip. This paper focuses on an innovative approach to automatically generate breakpoint modules by means of a breakpoint description language. This language is illustrated using an example, and experimental results are presented that show the efficiency and effectiveness of this new method for generating breakpoint hardware.

Philips has adopted a modular manufacturing test strategy for its SOCs that are part of the Nexperia/spl trade/ home platform. The on-chip infrastructure that enables modular testing consists of wrappers and test access mechanisms (TAMs). Optimizing that infrastructure minimizes the test application time and helps to fit the test data into the ATE vector memory. This paper presents the test architecture design for the chiplet-based PNX8550, the most complex Nexperia/spl trade/ SOC designed to date. Significant savings in test time and TAM wires could be obtained with the help of TR-ARCHITECT, an in-house tool for automated design of SOC test architectures.

International audience

Most system-on-chips (SOCs) today contain hierarchical cores that have multiple levels of design hierarchy. An efficient wrapper design for hierarchical cores is necessary to facilitate modular testing of SOCs. In most of the prior work on wrapper design for embedded cores, all the cores are assumed to have a flattened hierarchy. In this paper, we present a hierarchical core model and a generic IEEE P1500-compliant wrapper architecture for hierarchical cores. We assume that the embedded cores within the hierarchical cores are hard cores, since they are wrapped by the core vendor a priori and they have their own TAM architecture. Unlike prior wrapper design methods that assume a single test mode for hierarchical core wrappers, we present a general architecture for hierarchical core wrappers and describe various modes of operation of the wrapper. We design reconfigurable wrappers for hierarchical cores that can operate efficiently in all the test modes, thereby minimizing the overall time required to test the hierarchical core for any given TAM width. We propose a heuristic approach to solve the problem of hierarchical core wrapper design, and present experimental results for two hierarchical cores present in an ITC'02 benchmark SOC.

This article deals with the design of on-chip architectures for testing large system chips (SOCs) for manufacturing defects in a modular fashion. These architectures consist of wrappers and test access mechanisms (TAMs). For an SOC with specified parameters of modules and their tests, we design an architecture that minimizes the required tester vector memory depth and test application time. In this article, we formulate the test architecture design problems for both modules with fixed- and flexible-length scan chains, assuming the relevant module parameters and a maximal SOC TAM width are given. Subsequently, we derive a formulation for an architecture-independent lower bound for the SOC test time. We analyze three types of TAM under-utilization that make the theoretical lower bound unachievable in most practical architecture instances. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and TestRail architectures with either serial or parallel test schedules. Experimental results for the ITC'02 SOC Test Benchmarks show that, compared to manual best-effort engineering approaches, we can save up to 75% in test times, while compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.

This paper deals with the design of test architectures for modular SOC testing. These architectures consist of wrappers and TAMs (test access mechanisms). For a given SOC, with specified parameters of modules and their tests, we design architectures which minimize the required ATE vector memory depth and test application time. In this paper, we formulate the problems of test architecture design both for modules with fixed- and flexible-length scan chains. Subsequently, we derive a formulation of an architecture-independent test time lower bound for SOCs and list the lower bound values for the 'ITC'02 SOC test benchmarks'. We present a novel architecture-independent heuristic algorithm that effectively optimizes the test architecture for a given SOC. The algorithm efficiently determines the number of TAMs and their widths, the assignment of modules to TAMs, and the wrapper design per module. We show how this algorithm can be used for optimizing both test bus and testrail architectures with serial and parallel test schedules. Experimental results for the 'ITC'02 SOC test benchmarks' show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.

To debug a digital chip with a scan-based debug methodology, the chip is stopped at a certain point in time in the application. The state of the flip-flops and the memory elements is observed and compared with the simulation results. If the chip contains multiple clock domains then these clock domains must be stopped simultaneously, otherwise some of the elements in one or more of the clock domains will capture old data. The phenomenon of capturing old data is called data invalidation. This paper describes the data invalidation problem in depth and presents a data invalidation detector circuit. An automated hierarchical data invalidation analysis tool named DIAna is also presented. By means of experimental results for two industrial SoCs, we show the amount of data invalidation that can occur during silicon debug.

We present a two-step solution to the problem of test resource optimization for multi-site testing of embedded-core-based SOCs. In step 1, an efficient technique based on enhanced rectangle packing is used to design the wrapper/TAM (test access mechanisms) architecture such that the SOC test suite fits in a single ATE memory load. Furthermore, the total TAM width for the SOC is minimized, thereby reducing routing complexity and hardware cost. Minimum TAM width directly leads to the minimization of the number of ATE channels used, thus enabling multi-site testing. In step 2, test scheduling is performed such that "idle" bits appearing between core tests on ATE channels are moved to the end of each channel. This reduces the memory depth allocated to the channels from the pool of ATE memory. The saved memory can be mapped to the remaining ATE channels to test other SOCs, thereby further facilitating multi-site testing. We present experimental results on our technique for five benchmark SOCs.

In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained using the experiences gained from two large Philips system chips that each utilize core-based design and test, and scan-based silicon debug. The results of an area-cost evaluation of the presented architecture for these two large system chips are also presented.

A test architecture for an SOC consists of a number of Test Access Mechanisms that connect to wrapped cores. This paper presents a new test architecture, named the TestRail Architecture, that is a hybrid form of the known Daisychain and Distribution Architectures. An important characteristic of the TestRail Architecture is that it allows for efficient testing of both the cores as well as the core-external circuitry. We present two alternative optimization algorithms for the TestRail Architecture, that minimize the total core-internal test time of the cores in the SOC. These algorithms handle both cores with fixed-length and flexible-length scan chains. Experimental results on three industrial benchmark SOCs show that, compared to previous publications, we obtain comparable or better test times at drastically reduced compute times.

A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (TAM), the core test wrapper forms the test access infrastructure to embedded reusable cores. Various company-internal as well as industry-wide standardized but scalable wrappers have been proposed. This paper deals with the design of such core test wrappers. It gives a general architecture for wrappers, and describes how a wrapper can be built up from a library of wrapper cells which are selected on basis of the terminal types of the core. We show that the ordering and partitioning of wrapper cells and core-internal scan chains over TAM chains determine the test time of the core. An heuristic approach for the NP-hard problem of partitioning the TAM chain items for minimal test time is presented and its usage is illustrated by means of an example. Finally we sketch how wrapper generation and verification can be automated.