Two testable reversible logic gates are proposed in this paper. These gates can be used to implement reversible digital circuits with various levels of complexity. The major feature of these gates is that they provide online-testability for circuits implemented using these gates. The application of these gates in testable ripple carry, carry-skip adders and MCNC benchmark circuits have been illustrated.

The use of very deep submicron technology makes VLSI-based digital systems more susceptible to transient or soft errors, and thus compromises their reliability. This paper proposes an FPGA architecture inspired by the human immune system that allows tolerance of transient errors. The architecture is composed of a two-dimensional array of identical functional cells with different genetic codes. These codes are chosen based on the required functions to be performed by the functional cells. An error in a FPGA based digital system designed using the proposed architecture is treated as an antigen by the system. Using its distributed defense mechanism the system heals itself from the effect of the error. A major advantage of this architecture is that, the outputs of functional cells are connected to the inputs of other physically adjacent functional cells without having to go through complicated routing. Thus, lengthy communication paths between cells are avoided.

This paper presents hardware-based techniques for transient and permanent fault injection in VHDL descriptors of both combinational and sequential digital circuits. The designer can choose the fault injection rate, which may vary from 100% (permanent fault) down to 0.01% (transient fault).

Fault tolerance requires the inclusion of redundant information. In this paper an on-line error detecting adder is presented in which the redundant information serves a dual purpose. It provides fault tolerance during the arithmetic operations while also providing a method by which addition is constrained to become a constant delay operation regardless of the word size of the operands.

This paper presents a technique to improve verification at the VHDL level of digital circuits by means of a specially designed fault injection block. The injection technique allows incorporation of both transient and permanent faults to varying levels of VHDL hierarchy, and helps in verifying the performance of a testable system. 1.

An approach for designing state machines that have built-in on-line and off-line testability is proposed. The next state logic is designed using transmission gates and tri-state buffers only. The resulting machines have scan-in/scan-out capability that allows off-line testing of the next state logic. The on-line testing capability for erroneous state transitions is achieved by EX-ORing the outputs of two registers that store the current and the next state of a machine, and checking for even parity at the outputs of the EX-OR gates.

In recent years, a number of logic design techniques for look-up table (LUT) based FPGAs have been proposed. However, none of these address issues such as fault detection or testability. This paper presents an algorithm which maps optimized Boolean expressions into look-up table based FPGAs. This mapping automatically incorporates testability features into designs, allowing on-line detection of faults within a FPGA. This is accomplished by utilizing a unique set of cells to implement a design. These cells operate on the premise of a two-rail checker, thus producing both the normal and complemented output when a cell is operating correctly, and two outputs of the same value in the presence of a fault. Faults generated in an intermediate cell is propagated to the final outputs, thus allowing on-line testability of a FPGA-based logic system.

This paper presents a new algorithm to generate test sets for single stuck-at faults, which also detect all multiple stuck-at faults in fan-out-free circuits. This algorithm derives the test set for each node in a fan-out-free circuit by calculating the output count of the node. The output count indicates the number of test patterns needed to check for all faults in the corresponding subcircuit. The fan-out-free circuit can be any combination of AND, OR, NOT, NAND, and NOR gates.

This paper presents a technique for designing self-checking logic circuits by using residue codes. There are no restrictions or assumptions made about the implementation of the circuit. For any single stuck-at fault that causes bi-directional error at the output, all pairs of faulty output lines that show bi-directional errors are identified. Based on the bi-directional dependency between the outputs, a minimum set of residue weights are assigned to the output lines so that any error at the outputs can be detected.

In this brief communication, we present a checker design for 1-out-of-3 code that satisfies partially strongly fault-secure and partially strongly code-disjoint (PSFS/PSCD) properties. It is more efficient in terms of number of gates and time delay than any previously proposed 1-out-of-3 code checkers in the literature.>

Presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit errors at the output. An input encoding algorithm and an output encoding algorithm that ensure that every fault at the input will either produce single bit error or unidirectional multibit errors at the output are proposed. If there are no input faults which produce bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.>

Presents a new technique for designing single stage fully complementary metal oxide semiconductor (FCMOS) and CMOS domino logic circuits so that they are totally self checking for all single s-off and s-on faults. It involves the encoding of the output of the circuit in an error detecting code. CMOS circuits designed using the technique have two outputs. Two of the combinations (01,10) are considered to be valid code-words. The circuit is augmented such that any stuck-off (stuck-on) fault in the modified circuit produces a non-valid output 11(00), thus ensuring automatic fault detection.>

A new scheme for detecting single and multibit (unidirectional and bidirectional) errors using residue codes has been proposed. This procedure has been applied to circuits with outputs up to 8 bits. It has been shown that about 99% of all multibit errors can be detected using this scheme.>

An efficient technique for designing a totally self-checking checker for 1/n code (n>3) with minimum possible gate delay is proposed. The checker consists of a 1/n to k/2k translator and a k/2k code checker. The translator is implemented using a NOR array and checker using a NOR-NOR PLA. The design technique is applicable for all but a few values of n. It has been shown that the checkers constructed using the proposed technique occupy minimum or near-minimum chip area depending on the value of n. This new technique also has the advantage over existing ones in terms of speed or hardware.>

It is generally agreed now that the major portion of faults in logic system are not of permanent nature. Current testing strategies are incapable of detecting nonpermanent faults. The characteristics of such faults requires that logic circuits be designed in a way so that if there is a fault in the circuit, its effect will be detected during the normal operation of the circuit, i.e. the circuits be self-checking. In this paper the authors propose two rules based on the mode 3 residue coding scheme for designing circuits for online error detection.>

Recently D.J. Lin and B. Bose, (1988) proposed a class of t error correcting and d unidirectional error detecting codes (t-EC/d-UED codes) where d>t. The authors refine the codes in such a way that the error detecting capability of the resulting codes is considerably better than the existing codes in many cases. The decoding algorithm is described. The proposed codes are compared to the Lin-Bose codes.>

A method for constructing a class of t-error correcting and all unidirectional error-detecting systematic codes is proposed. These codes have been shown to be more efficient than codes constructed using other methods proposed in the literature. In a special case, the code constructed is the Berger code.>