This paper presents a system for parallel operation of functional units in a processor that is under microprogram control. Specifically, for a multiple functional unit computer this new technique allows concurrent operation of the functional units without requiring hardwired instructions. A new interlock system for ordering execution of instructions is also presented. Two applications are shown: one to a three functional unit serial processor and one to an array processor. The mechanism allows holding instructions until the data on which they are to operate are ready and is a microcode version of that used on the IBM 360/91 or on the CDC 6600. This concurrency can be under either hardware, firmware, or software control.

Memory has always been a major factor in determining the cost of a computer system. Many schemes have been proposed for reducing memory cost without degrading system performance or increasing system cost or complexity significantly. This paper presents a particular data type that may have been used occasionally by programmers who have had to simulate floating-point hardware by software. This new data type is useful in large scientific problems and may be able to serve as a replacement for floating-point data type on special-purpose processors. Its hardware implementation on orthogonal and pipeline processors is discussed in detail and the implications of these implementations for a programming language (APL) (Iverson's language) are examined.