This article presents MP-Tomasulo, a dependency-aware automatic parallel task execution engine for sequential programs. Applying the instruction-level Tomasulo algorithm to MPSoC environments, MP-Tomasulo detects and eliminates Write-After-Write (WAW) and Write-After-Read (WAR) inter-task dependencies in the dataflow execution, therefore to operate out-of-order task execution on heterogeneous units. We implemented the prototype system within a single FPGA. Experimental results on EEMBC applications demonstrate that MP-Tomasulo can execute the tasks out-of-order to achieve as high as 93.6% to 97.6% of ideal peak speedup. A comparative study against a state-of-the-art dataflow execution scheme is illustrated with a classic JPEG application. The promising results show MP-Tomasulo enables programmers to uncover more task-level parallelism on heterogeneous systems, as well as to ease the burden of programmers.

This paper summarizes a special session on multi-core/multi-processor system-on-chip (MPSoC) programming challenges. Wireless multimedia terminals are among the key drivers for MPSoC platform evolution. Heterogeneous multi-processor architectures achieve high performance and can lead to a significant reduction in energy consumption for this class of applications. However, just designing energy efficient hardware is not enough. Programming models and tools for efficient MPSoC programming are equally important to ensure optimum platform utilization. Unfortunately, this discipline is still in its infancy, which endangers the return on investment for MPSoC architecture designs. On one hand there is a need for maintaining and gradually porting a large amount of legacy code to MPSoCs. On the other hand, special C language extensions for parallel programming as well as adapted process network programming models provide a great opportunity to completely rethink the traditional sequential programming paradigm for sake of higher efficiency and productivity. MPSoC programming is more than just code parallelisation, though. Besides energy efficiency, limited and specialized processing resources, and real-time constraints also growing software complexity and mapping of simultaneous applications need to be taken into account. We analyze the programming methodology requirements for heterogeneous MPSoC platforms and outline new approaches.

Block processing using look-ahead is a useful technique for increasing the parallelism in recursive filtering. This paper attempts to give a straightforward approach to transform a class of existing efficient structures of denominator-separable 2-D filters for the purpose of block processing by using a look-ahead approach (pipeline interleaving). The property of low roundoff noise and the absence of overflow limit cycles are preserved by the transformation. The degree of the concurrency is further increased linearly without additional computational overhead by incorporating the "line block processing" technique.

2-D denominator-separable digital filters represent an important subclass of 2-D recursive digital filters. Various implementations have been suggested. In this paper, to derive new realizations the fact is used that, different from the case of a general 2-D digital filter, a denominator-separable filter can be developed as an orthonormal expansion. The orthonormal basis has been chosen such that the components can be realized by a normalized lattice structure, proposed in the 1-D case by Gray and Markel (1975). The new realization inherits all properties of the normalized lattice structure: low roundoff noise, freedom from overflow limit cycles.>

A straightforward technique using a 1-D to 2-D spectral transformation is proposed for designing 2-D IIR (infinite impulse response) quarter-plane digital filters. Starting with the specification on the magnitude-frequency response of the filter, an optimal extended McClellan transformation is developed. Then a 1-D equiripple IIR digital filter is designed. Introducing the transformation into the 1-D IIR filter, the 2-D IIR quarter-plane digital filter. It is shown how to design 2-D digital filters having a circularly symmetric magnitude-frequency response using this technique, and it is demonstrated that the resulting filter possesses a very good response. The specifications on the frequency response are satisfied with a small error variation, and the stability is always guaranteed without a 2-D stabilization procedure.>