Demo Data from VLDB 2026 / reviewers in the wild / expert
Ahmed E. Barbour
dblp:50/7034
· DBLP profile ↗
5ranked-venue papers
2as first author
0since 2021 · last 1993
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 54% Electronic design automation · 46% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance › fault-tolerant design
fault-tolerant circuit design |
0.0 | 1 | 1992 | Solutions to the Minimization Problem of Fault-Tolerant Logic Circuits · IEEE Trans. Computers 1992 |
Electronic design automation › logic synthesis › circuit optimization
gate-count minimization |
0.0 | 1 | 1992 | Solutions to the Minimization Problem of Fault-Tolerant Logic Circuits · IEEE Trans. Computers 1992 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1992 | Solutions to the Minimization Problem of Fault-Tolerant Logic Circuits · IEEE Trans. Computers 1992 |
Hardware reliability and fault tolerance
fault-tolerant design |
0.0 | 1 | 1989 | A General, Constructive Approach to Fault-Tolerant Design Using Redundancy · IEEE Trans. Computers 1989 |
Hardware reliability and fault tolerance › redundancy › modular redundancy
triple modular redundancy |
0.0 | 1 | 1989 | A General, Constructive Approach to Fault-Tolerant Design Using Redundancy · IEEE Trans. Computers 1989 |
Methods — techniques the papers use, named apart from their topics
block design theory · 0.0approximation algorithm · 0.0mathematical block theory · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1993 | Testability and test generation for majority voting fault-tolerant circuits
Charles E. Stroud, Ahmed E. Barbour |
J. Electron. Test. | 2 |
| 1992 | Solutions to the Minimization Problem of Fault-Tolerant Logic CircuitsabstractThe optimization problem of a general approach for designing fault-tolerant circuits is investigated. The gate minimization problem is solved so that optimal design with respect to the numbers of gates and levels is obtained. The concept and properties of block design are used to formulate, solve for, and construct the optimal form. The gate minimization problem for a fault-tolerant circuit is formulated and a lower bound to the number of minimum gates for any design is established. For certain design parameters, explicit minimum solutions are given. When no minimum solution is found, sets of explicit block designs which produce near-minimum designs are characterized. In both cases, minimum and near-minimum algorithms which generate the blocks required to construct the logic for fault-tolerant circuits in linear times are devised. If a block design does not have any connection with the minimum or near-minimum classes, an approximation algorithm which generates near-minimum blocks in a polynomial time is suggested.> Ahmed E. Barbour |
IEEE Trans. Computers | 1 |
| 1990 | Parallel Processing and Hardware Acceleration for Synthesis of VLSI Devices from Behavioral Models
Charles E. Stroud, Ahmed E. Barbour |
ICPP (1) | 2 |
| 1989 | Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant CircuitsabstractThe necessary conditions for designing testable static redundancy system-level fault-tolerant circuits are derived. In addition, algorithms are proposed for the efficient generation of test patterns for fault-tolerant circuits designed to satisfy these testability conditions. The test generation algorithm has been incorporated with an algorithm for the construction of majority voting devices and automated to produce a software package that generates testable fault-tolerant circuits along with test patterns to test the resultant circuit completely. As input, the algorithm requires a testable original circuit, along with an associated set of test patterns and the desired design parameters E, R, and K.> Charles E. Stroud, Ahmed E. Barbour |
ITC | 2 |
| 1989 | A General, Constructive Approach to Fault-Tolerant Design Using RedundancyabstractThe use of redundancy to attain a fault-tolerant system design is described. Specifically, a general theory of redundancy is proposed that allows the design of fault-tolerant structures at the system-level, gate-level, or both. The theory accounts for classic approaches to redundant design such as TMR, NMR, and quadded and interwoven logics. It is shown that, by using mathematical block theory, it is possible to describe complex interconnections of redundant elements in a simple, straightforward fashion. Comparisons are made with other approaches to redundant design.> Ahmed E. Barbour, Anthony S. Wojcik |
IEEE Trans. Computers | 1 |