Demo Data from VLDB 2026 / reviewers in the wild / expert
Matthew R. Johnson 0003
dblp:50/7115-3
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2010
0000-0003-3953-8898ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2Software engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Hardware accelerators and domain-specific architectures · 67% Parallel and multicore computing · 33% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
many-core accelerator |
0.1 | 1 | 2009 | Rigel: an architecture and scalable programming interface for a 1000-core accelerator · ISCA 2009 |
Parallel and multicore computing
parallel programming models |
0.1 | 1 | 2009 | Rigel: an architecture and scalable programming interface for a 1000-core accelerator · ISCA 2009 |
Hardware accelerators and domain-specific architectures › accelerator architecture
programmable accelerator |
0.1 | 1 | 2009 | Rigel: an architecture and scalable programming interface for a 1000-core accelerator · ISCA 2009 |
Methods — techniques the papers use, named apart from their topics
hierarchical core organization · 0.1bulk-synchronous task scheduling · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | WAYPOINT: scaling coherence to thousand-core architecturesabstractIn this paper, we evaluate a set of coherence architectures in the context of a 1024-core chip multiprocessor (CMP) tailored to throughput-oriented parallel workloads. Based on our analysis, we develop and evaluate two techniques for scaling coherence to thousand-core CMPs. We find that a broadcast-based probe filtering scheme provides reasonable performance up to 128 cores for some benchmarks, but is not generally scalable. We propose a broadcast-collective network for accelerating probe filter misses, which extends scalability but falls short of supporting 1024 cores. We find that a sparse directory with an invalidate-on-evict policy can work well for many throughput-oriented workloads. However, the on-die structures required to achieve good performance carry a large performance and power overhead. To achieve thousand-core scalability with smaller and less associative sparse directories, we introduce WayPoint, a mechanism that increases directory associativity and capacity dynamically. Using less than 3% of total die area, Way-Point achieves performance within 4% of an infinitely large on-die directory. John H. Kelm, Matthew R. Johnson 0003, Steven S. Lumetta, Sanjay J. Patel |
PACT | 2 |
| 2009 | Rigel: an architecture and scalable programming interface for a 1000-core acceleratorabstractThis paper considers Rigel, a programmable accelerator architecture for a broad class of data- and task-parallel computation. Rigel comprises 1000+ hierarchically-organized cores that use a fine-grained, dynamically scheduled single-program, multiple-data (SPMD) execution model. Rigel's low-level programming interface adopts a single global address space model where parallel work is expressed in a task-centric, bulk-synchronized manner using minimal hardware support. Compared to existing accelerators, which contain domain-specific hardware, specialized memories, and/or restrictive programming models, Rigel is more flexible and provides a straightforward target for a broader set of applications. John H. Kelm, Daniel R. Johnson, Matthew R. Johnson 0003, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel |
ISCA | 3 |