Abstract Modern System-on-Chip (SoC) designs integrate various embedded instruments and proprietary data to support critical operations such as testing, diagnosis, and in-field health monitoring. The IEEE Std. 1687 (IJTAG) is widely adopted to provide efficient and flexible access to these on-chip instruments. However, its reconfigurable nature exposes a significant attack surface, making it vulnerable to advanced security threats, including machine learning, differential analysis, and power analysis attacks, which can extract Chip IDs and cryptographic keys. To enhance the security of the IJTAG architecture, a secure access protocol has been proposed in the literature. In this secure access scheme, a random number generator produces a bitstream, and whenever a predefined template matches, a key bit is inserted into the bitstream; this process continues until all key bits are embedded. However, the reliance on a single static template renders the scheme predictable and susceptible to key recovery. To overcome this limitation, we propose a multi-dynamic template based secure access protocol , where multiple templates are employed for key insertion. For each comparison, the specific template is dynamically selected based on the last generated bit of the bitstream, thereby introducing randomness into the embedding process and obfuscating adversarial analysis. The experimental evaluation demonstrates that, with eight templates, the proposed protocol reduces machine learning attack accuracy from 98.31 to 0.0002%, increases the complexity of differential analysis by extending the key retrieval time from 3 ms to approximately $$ 1.67 \times 10^{10} $$ 1.67 × 10 10 years, and renders power analysis attacks completely infeasible. In addition, the proposed scheme significantly reduces the bitstream length required for key insertion. For instance, with a 16-bit template and a 256-bit key, the required bitstream length decreases from 16.6 million to 12.8 thousand, while for a 24-bit template and a 256-bit key, it decreases from 4.2 billion to 57.2 thousand, while maintaining security. Furthermore, hardware synthesis on ITC’16 IJTAG benchmarks confirms negligible implementation cost, with area overheads of only 1.65% and 1.53% for the TreeFlatEx and TreeBalanced benchmarks, respectively. These results demonstrate that the proposed protocol provides scalable, resource-efficient and robust protection for IJTAG-enabled SoCs against state-of-the-art attacks.

The increasing complexity and core count of modern System-on-Chips (SoCs) have raised significant concerns regarding test time and test data volume. Despite advancements in SoC design, the physical size of SoCs remains relatively constant, imposing stringent constraints on the number of additional I/O pins to support parallel testing. Furthermore, the disparity in scan chain lengths exacerbates these challenges due to padding requirements, which significantly increase the test data volume. Recently, a novel test architecture, the Streaming Scan Network (SSN), has been introduced, which demonstrates a significant reduction in both test time and test data volume. However, the SSN lacks robust security countermeasures, making it susceptible to threats such as unauthorized access and data tampering. To mitigate these threats, this article presents a lightweight and inherently secure solution that leverages the IJTAG Static Test Data Register (TDR) as a dual-functional module, ensuring both security and the preservation of the SSN’s original functionality. The experimental results demonstrate that the proposed countermeasure incurs 9.08%, 18.34%, 77.54%, and 167.28% less area overhead compared to the state-of-the-art Masking, NLFSR, UAU, and ROT countermeasures, respectively, while maintaining a security level equivalent to a 1024-bit key. Additionally, the proposed approach maintains low computational overhead and minimal authorization cycles, making it a scalable and practical solution for secure SoC testing.

Hardware Trojans (HTs) pose substantial security threats to Integrated Circuits (ICs), compromising their integrity, confidentiality, and functionality. Various HT detection methods have been developed to mitigate these risks. However, the limited availability of comprehensive HT benchmarks necessitates designers to create their own for evaluation purposes. Moreover, the existing benchmarks exhibit several deficiencies, including a restricted range of trigger nodes, susceptibility to detection through random patterns, lengthy HT instance creation and validation process, and a limited number of HT instances per circuit. To address these limitations, we propose a Compatibility Graph assisted automatic Hardware Trojan insertion framework for HT benchmark generation. Given a netlist, this framework generates a design incorporating single or multiple HT instances according to user-defined properties. It allows various configurations of HTs, such as a large number of trigger nodes, low activation probability and large number of unique HT instances. The experimental results demonstrate that the generated HT benchmarks exhibit exceptional resistance to state-of-the-art HT detection schemes. Additionally, the proposed framework achieves an average improvement of 37815.7x and 989.4x over the insertion times of the Random and Reinforcement Learning based HT insertion frameworks, respectively.

Intestinal Parasitic Infections (IPIs) continue to pose a significant global health challenge, disproportionately affecting vulnerable populations and straining healthcare systems, particularly in resource-constrained environments. The accurate and automated detection of parasitic eggs in microscopic images is critical for timely diagnosis and treatment. However, Intra class Variation (ICVs) in egg morphology, influenced by developmental stage variability, often leads to misclassifications with high confidence in deep learning models. To address this challenge, the Augmentation-Based Supervised Target Learning (ASTL) approach is introduced to enhance the models robustness against developmental stage variability. In addition, the IPI-CVx framework is proposed, integrating ASTL with a preprocessing pipeline to mitigate data heterogeneity and improve detection accuracy and reliability. Experimental results demonstrate that IPI-CVx surpasses state-of-the-art models, achieving 97. 3% mean average precision (mAP), 97. 6% mean intersection over union (mIoU) and a 97. 9% F1 score. By effectively addressing ICVs and reducing misclassifications that have high confidence, the proposed framework enhances robustness and interpretability, fostering trust and transparency for clinical deployment.

Modern advancements in hardware implementation of Deep Neural Networks (DNNs) have underscored the need for efficient and accurate nonlinear activation function approximations to reduce computational complexity in resource-constrained environments like FPGA. Traditional methods face challenges in achieving an optimal balance between accuracy and hardware efficiency. To address this, we propose PSO-GP, an automated framework that formulates the approximation as an optimization problem. In this framework, Genetic Programming (GP) approximates complex functions in linear functions, while Particle Swarm Optimization (PSO) identifies optimal interval partition to minimize error. The experimental results demonstrate that PSO-GP significantly improves accuracy and reduces hardware overhead compared to state-of-the-art methods.

As System-on-Chip (SoC) architecture becomes increasingly complex, the need for secure and efficient testing methodologies have grown. Recently, the Streaming Scan Network (SSN) was introduced as a testing infrastructure to address the limitations of conventional scan-based architectures in handling complex SoCs. However, SSN architecture presents significant security risks if access control mechanisms are not implemented. Malicious users could exploit the SSN to extract sensitive information from the SoC, posing a serious threat to system security. To address these vulnerabilities, this paper proposes a secure SSN architecture that employs test vector encryption and test response masking. Further, test authorization key is needed to access the test responses. The proposed solution secures the SSN while keeping the functionality intact and additionally reduces the area overhead compared to existing schemes.

Logic locking has emerged as a crucial defense mechanism for securing ICs against threats such as IP theft, counterfeiting, and Hardware Trojans (HTs). However, advanced attacks like Boolean Satisfiability (SAT) attack have exposed vulnerabilities by exploiting scan-unlocked oracle to retrieve secret keys. To mitigate this risk, scan obfuscation techniques were introduced to secure scan access and enhance protection against SAT attack. However, ScanSAT attack has been shown to bypass these defenses, successfully retrieving secret keys even from scan-obfuscated circuits. Recently, a test authentication scheme combined with scan obfuscation has been proposed as a countermeasure against ScanSAT attack.This work presents an attack that employs a stealthy HT to subvert the security provided by the test authentication scheme. Our analysis demonstrates that the inserted Trojan not only facilitates the execution of the ScanSAT attack but also eludes detection by the state-of-the-art Hardware Trojan detection techniques. These results highlight critical vulnerabilities in current IC security measures, emphasizing the need for resilient defenses against increasingly sophisticated attacks.

Abstract Billboard Advertisement is a popular out-of-home advertising technique adopted by commercial houses. Companies own billboards and offer them to commercial houses on a payment basis. Given a database of billboards with slot information, we want to determine which k slots to choose to maximize the influence. We call this the Influential Billboard Slot Selection ( $$\textsc {IBSS}$$ IBSS ) Problem and pose it as a combinatorial optimization problem. We show that the influence function considered in this paper is non-negative, monotone, and submodular. The incremental greedy approach based on the marginal gain computation leads to a constant factor approximation guarantee. However, this method scales very poorly when the size of the problem instance is very large. To address this, we propose a spatial partitioning and pruned submodularity graph-based approach divided into the following three steps: pre-processing, pruning, and selection. We analyze the proposed solution approaches to understand their time, space requirements, and performance guarantees. We conduct extensive experiments with real-world datasets and compare the performance of the proposed solution approaches with the available baseline methods. We observe that the proposed approaches lead to more influence than all the baseline methods within a reasonable computational time.

ABSTRACT We propose a Essential Secret Image Sharing scheme using Linear Homogeneous Recurrence Relation and polynomials for sharing a grayscale or color secret image in the semihonest model. In our scheme, the dealer generates essential and nonessential shares of a secret image. A combiner needs shares to reconstruct the secret image, where at least are essential shares. Unlike most state‐of‐the‐art schemes restricting to be equal to , our scheme also allows for . This merit makes reconstruction possible even if up to essential shares are unavailable. Additionally, compared to state‐of‐the‐art schemes, our scheme offers substantial reductions in share sizes—by factors formed from , , , and . Thus, with this reduced size of shares, leading to reduced share storage costs, our scheme has a broader range of applications, including those with limited budgets. Moreover, in cases where , the shares generation period in our scheme, during which an adversary can potentially steal the secret image from the dealer, is at least 42% shorter than that in the state‐of‐the‐art scheme supporting .

Main memory plays a pivotal role in the storage of computational data in a wide range of applications, including highly sensitive assets such as banking transactions, cryptographic keys, and user credentials. However, memory systems remain vulnerable to advanced physical and side-channel attacks, including cold boot attacks that exploit residual data after power-down. To mitigate such risks, Intel’s DDR3 memory scrambler uses a Linear Feedback Shift Register (LFSR)-based stream cipher to obscure memory contents. Nevertheless, this mechanism has been shown to be susceptible to stencil attack, a cold boot technique that reconstructs the scrambling key by leveraging the linear and periodic nature of the keystream. This article proposes a novel, lightweight, and secure scrambling architecture based on a generic LFSR designed to enhance the security of DDR3 memory against cold boot attacks. The proposed generic LFSR-based mechanism eliminates differential keystream periodicity by introducing an address- and seed-dependent LFSR structure, thereby rendering differential key recovery techniques computationally infeasible. Furthermore, unlike traditional AES-based memory encryption that incurs high latency and area overhead, the proposed approach achieves comparable security guarantees with low hardware complexity and zero access latency. The hardware implementation results on the Xilinx VCU118 FPGA show that the proposed scheme consumes only 252 LUTs, 256 registers and 104 slices, comparable to the Intel DDR3 scrambler, while offering superior resilience against the cold boot, warm boot, and probing attacks. These results demonstrate the practicality of the proposed scheme for secure memory systems in resource-constrained environments.

Change point detection (CPD) is a valuable technique in time series (TS) analysis, which allows for the automatic detection of abrupt variations within the TS. It is often useful in applications such as fault, anomaly, and intrusion detection systems. However, the inherent unpredictability and fluctuations in many real-time data sources pose a challenge for existing contemporary CPD techniques, leading to inconsistent performance across diverse real-time TS with varying characteristics. To address this challenge, we have developed a novel and robust online CPD algorithm constructed from the principle of discriminant analysis and based upon a newly proposed between-class average and variance evaluation approach, termed B-CAVE. Our B-CAVE algorithm features a unique change point measure, which has only one tunable parameter (i.e. the window size) in its computational process. We have also proposed a new evaluation metric that integrates time delay and the false alarm error towards effectively comparing the performance of different CPD methods in the literature. To validate the effectiveness of our method, we conducted experiments using both synthetic and real datasets, demonstrating the superior performance of the B-CAVE algorithm over other prominent existing techniques.

The scan design is a widely accepted technique employed to enhance the testability of VLSI designs. However, it introduces exploitable side channels that allow attackers to illicitly access confidential information within crypto-cores. To address this concern, several countermeasures have been proposed. Among these countermeasures, two specific types include obfuscation and encryption of the test response at the Scan-Out (SO) port, rendering the test response inaccessible for analysis by potential attackers. This paper proposes a scan attack that effectively retrieves the AES encryption key, even in the presence of both obfuscation and encryption countermeasures.

Abstract We propose a novel secret image sharing scheme with ciphertext‐based share authentication (SISS‐CSA) for sharing grayscale and color secret images in the malicious model. In SISS‐CSA, the dealer and each participant, individually acting as a combiner, can identify each invalid share received from the malicious participant(s) before using it to reconstruct the secret image. This capability, which most comparable schemes lack, prevents reconstructing an incorrect secret image. In SISS‐CSA, the asymptotic time complexities of operations executed by the dealer in the shares generation phase and executed by each combiner in the secret image reconstruction phase are and , respectively. Here, is the number of grayscale values in the secret image, is the number of generated shares, and is the threshold number of shares required for reconstructing the secret image. These asymptotic time complexities and the size of additional information each combiner stores for identifying invalid share(s) are comparatively lesser than those in the state‐of‐the‐art schemes. Furthermore, we obtain a maximum of reduction in the size of additional information each combiner stores for share authentication using the ciphertext‐based share authentication compared to using the standard SHA‐256. To the best of our knowledge, none of the related share authentication approaches achieves this much reduction. We prove the properties of SISS‐CSA using theoretical analysis. We also provide experimental results validating the implications of theoretical analysis corresponding to asymptotic time complexities and the random nature of shares.

Now-a-days, billboard advertisement has emerged as an effective outdoor advertisement technique. In this case, a commercial house approaches an influence provider for a specific number of views of their advertisement content on a payment basis. If the influence provider can satisfy this then they will receive the full payment else a partial payment. If the influence provider provides more or less than the demand then certainly this is a loss to them. This is formalized as ‘Regret’ and the goal of the influence provider will be to minimize the ‘Regret’. In this paper, we propose simple and efficient solution methodologies to solve this problem. Efficiency and effectiveness have been demonstrated by experimentation.

Test data volume and test time have become a major concern in the testing of complex System on Chips (SoCs). This is due to the fact that the complexity, as well as the number of cores, keeps increasing while the physical size of SoCs remains relatively constant. Consequently, there is limited space available for additional IO pins for scan purposes, which restricts the ability to test multiple cores in parallel. Moreover, testing multiple cores concurrently with different scan chain lengths further increases the test data volume and test time due to the padding. To mitigate the above problems, a new testing architecture called a Streaming Scan Network (SSN) has been recently developed. It is a bus-based architecture that enables the testing of multiple cores with reduced test data volume and test time. However, the SSN-based architecture lacks essential security features, rendering it susceptible to various security threats, including unauthorized user access, as well as data sniffing and alteration attacks. In this paper, a simple, lightweight, inherently secure solution is proposed to counteract the above security threats. The proposed approach involves leveraging IJTAG static registers to incorporate security features into the SSN architecture. The proposed solution keeps the SSN functionality intact and incurs a minimal area overhead as compared to the existing solutions.

Scan design is the most commonly used technique to ensure high test coverage in contemporary chips. However, attackers may use it as a trapdoor to gain access to the chip internals. Thus, it affects the overall chip security. Several techniques have been proposed to protect sensitive data from hackers. Recently, a countermeasure has been proposed that obfuscates the scan data using a test key. This scheme looks simple and effective against all the existing scan-based attacks. However, a detailed analysis of the scheme reveals that it is vulnerable to scan-based side-channel attacks. In this paper, it is shown that the test key could be retrieved successfully, and hence the security provided by this scheme is rendered ineffective. To address this vulnerability, a countermeasure is also proposed.

Modern VLSI circuits feature various embedded instruments that support non-functional features, e.g., test/debug, diagnosis, post silicon validation, in-field maintenance, etc. The IEEE Std. 1687 (IJTAG) facilitates efficient access to these on-chip instruments using a special scan cell known as Segment Insertion Bit (SIB). Concomitantly, it provides a covert channel for potential intruders to gain unauthorized access to these embedded instruments and thus extract confidential data such as FPGA firmware, secret keys, etc. Thus, it is quite imperative to restrict access to embedded instruments. Various techniques are present in the literature for enhancing the security of IJTAG network. However, securing the test infrastructure at the cost of complex hardware resources is not always a feasible solution.In this paper, a new mechanism to secure the IJTAG network which is based on a new Inherently Secure SIB (ISSIB) is proposed. The proposed technique makes use of an LFSR that is formed using the update cell of the ISSIBs. The proposed scheme is simple to implement, highly scalable and provides high level of security against unauthorized access. In addition to that, the proposed scheme preserves the conventional IJTAG features and has negligible area overhead.

The modern-day SoCs have various instruments and proprietary data embedded on chip for test, diagnosis, post-silicon debug, in-field health monitoring, authentication, counterfeit detection, etc. The testing infrastructure such as IEEE Std. 1687 (IJTAG) is incorporated into the ICs for flexible access to these on-chip instruments. However, this standard can be illegitimately used by malicious users for instigating side-channel attacks. In order to improve the security of the IJTAG network, a secure access protocol based on Chip ID, access software and Locking SIB (LSIB) has been proposed. Although this protocol elevates the security of the IJTAG network, in recent works, it has been shown that the secure access protocol is vulnerable to machine learning attack and differential analysis attack. In this work, a new secure access protocol is proposed which is built over the existing secure access protocol. The proposed protocol uses multiple templates which are selected randomly for embedding the key bits. It is shown that the proposed protocol can mitigate the efficacy of machine learning attack and differential analysis attack significantly. Moreover, it is simple to implement and incurs a marginal overhead in terms of area.

The IEEE 1687 standard, which is commonly used for efficient access of on-chip instruments, could be exploited by an intruder and thus needs to be secured. One of the techniques to alleviate the vulnerability of 1687 network is to use a secure access protocol that is based on licensed access software, Chip ID and locking SIB. A licensed access software is generally used to gain control of the embedded instruments and use them as per requirement.

Image distortion is a problem due to wide field-of-view cameras, and camera calibration is a fundamental step in various applications such as image undistortion, 3D reconstruction, and camera motion estimation to overcome this problem. In image calibration, intrinsic camera parameters such as focal length and distortion are estimated. The quality of the undistorted/enhanced image depends on the correctness of focal length and distortion. However, existing methods consist of two approaches: checkerboard, which requires manual interaction, and others are deep learning approaches. Most Deep Learning approaches are based on the Convolution Neural Network (CNN) framework, and it fails to capture the long-term dependency in a distorted image. This paper proposes a fully automated EnsembleNet method to infer the focal length and distortion parameters to overcome this problem. The proposed model extracts various contexts (local patches) by exploiting ViT(Vision Transformer) and spatial features from various CNN-based models using a single input image. The proposed model uses the differential evolution (DE) approach to learn the ensemble weights. The experiments show that the proposed EnsembleNet outperforms the state-of-the-art deep learning-based models in terms of mean squared error.

In recent decennium, hardware security has gained a lot of attention due to different types of attacks being launched, such as IP theft, reverse engineering, counterfeiting, etc. The critical testing infrastructure incorporated into ICs is very popular among attackers to mount side-channel attacks. The IEEE standard 1687 (IJTAG) is one such testing infrastructure that is the focus of attackers these days. To secure access to the IJTAG network, various techniques based on Locking SIB (LSIB) have been proposed. One such very effective technique makes use of Security Linear Feedback Shift Register (SLFSR) along with LSIB. The SLFSR obfuscates the scan chain information from the attacker and hence makes the brute-force attack against LSIB ineffective.In this work, it is shown that the SLFSR based Locking SIB is vulnerable to side-channel attacks. A power analysis attack along with known-plaintext attack is used to determine the IJTAG network structure. First, the known-plaintext attack is used to retrieve the SLFSR design information. This information is further used along with power analysis attack to determine the exact length of the scan chain which in turn breaks the whole security scheme. Further, a countermeasure is proposed to prevent the aforementioned hybrid attack.

Today’s integrated circuits contain a large number and variety of embedded instruments that support testing, infield monitoring, post-silicon validation, etc. The IEEE Std. 1687 (IJTAG) provides efficient access to these embedded instruments by dynamically reconfiguring the IJTAG network. At the same time, it opens a backdoor for malicious users to steal sensitive information. Hence, access to embedded instruments through IJTAG must be restricted/secured. Various techniques have been proposed to prevent unauthorized access to the IJTAG network. One such very effective technique that improves the security of IJTAG network is a secure access protocol that uses licensed access software, Locking SIB (LSIB) and Chip ID. Although this technique is simple to implement and is very effective against scan attacks; however, it does not consider the power analysis attack.In this study, it is demonstrated that the security of the secure access protocol technique could be easily breached using a power analysis side-channel attack. The attack leads to unauthorized access to the embedded instruments which in turn could be used for various malicious purposes. Moreover, a countermeasure that mitigates the efficacy of power analysis attack significantly is proposed. It incurs a minimal area overhead and can be easily integrated into the existing secure access protocol.

In this paper we propose a wrapper based PSO method for gene selection in microarray datasets, where we gradually refine the feature (gene) space from a very coarse level to a fine grained one, by reducing the gene set at each step of the algorithm. We use the linear support vector machine weight vector to serve as the initial gene pool selection. In addition, we also examine integration of other filter based ranking methods with our proposed approach. Experiments on publicly available datasets, Colon, Leukemia and T2D show that our approach selects only a very small subset of genes while yielding substantial improvements in accuracy over state-of-the-art evolutionary methods.