Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture.

Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security technique to detect any HTHs present in the circuit by inserting tri-state buffers (TSB) in the ICs that inject the internal nets with weighted logic values during the test phase. This increases the transitions in the logic values of the nets within the IC, thereby stimulating any inserted HTH circuits. The TSBs are efficiently inserted in the IC considering various circuit parameters and testability measures to bolster the transitions in logic values of the nets throughout the IC while minimising the area overhead. Simulation results show a significant increase in transitions in logic values within HTH triggers using this method, thus aiding in their detection through side-channel analysis or direct activation of the payload.

Through silicon via (TSV)-based 3-D integrated circuit (3-D IC) has several advantages like high density, high bandwidth, and low-power consumption. However, many defects in TSV are evolved during the fabrication and bonding process. In practice, faulty TSVs tend to be clustered. Employing spare TSVs (s-TSVs) is an acceptable method for repairing faulty TSVs. This article introduces a tree-based TSV repair framework to utilize hardware resources more efficiently for a higher repair rate. The proposed architecture partitions the s-TSVs for a different level of redundancy sharing. Experimental results show that the proposed design consumes 11.01 μm2area per signal TSV to achieve 99.99% yield for 0.05% failure rate. The proposed architecture also exhibits a higher repair rate of 73.33% for heavily clustered faults. Moreover, for the same number of functional and s-TSVs, the proposed approach reduces the delay overhead efficiently compared to the prior works.

Digital microfluidic biochip is a revolutionizing platform to execute complex bioassay operations concurrently. Dependability is an important feature of digital microfluidic biochip which is used for many safety-critical applications, such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore to ensure the proper functionality of the biochip a robust offline and online testing is required. Testing can be done before manufacturing or concurrently with other bioassay operations. In this work, we are presenting an efficient parallel testing and diagnosis scheme to reveal the location of all the faulty electrodes. Most of the algorithms present in the literature are mainly focused on single fault identification. But the diagnosis of biochip with multiple faults is not addressed properly. Even some of the algorithms have incorrectly classified the non faulty electrode as a faulty electrode. Thus in this paper, we are mainly focusing on the detection of multiple faults, correctly and efficiently. Moreover, this testing method is capable to check the given biochip with other concurrently running bioassay operations.

Three-dimensional Integrated Circuit (3D IC) based on through silicon via (TSV) has brought a drastic change in the IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for the system operation. So, testing of TSV is essential for 3D IC. In this paper a cost-effective Built-in Self-Test (BIST) mechanism is proposed for the post-bond test of TSVs in 3D ICs. The test method aims at identifying single and multiple defective TSVs using low test time with minimum hardware. The time cycle needed for testing is calculated and is compared with previous proposed methods. The simulation result shows that the proposed BIST circuit is beneficial over prior BIST technology in terms of test time cycle and hardware requirement.

Three dimensional (3D) integration based on through-Silicon-Via (TSV) is currently evolving as an area of great interest in modern semiconductor industry. 3D integration provides higher performance, bandwidth and lower power consumption. But due to scaling in technology features these chips are more complex. Hence, testing of these 3D integrated circuits (ICs) is a challenging task. Effective test architecture design and optimization techniques are essential to minimize the manufacturing test cost. This paper addresses test architecture optimization and Design-for-Test (DfT) for 3D ICs. We design test wrapper for 3D SOC using minimum number of TSVs. Heuristic algorithms are proposed to minimize test time for 3D SOC. Also, TSVs for test access is limited due to small chip area. To address this issue, algorithms are proposed to minimize overall test time considering all possible partial stacks and complete stack for 3D IC with hard dies under TSV constraint. We next describe strategies to identify faulty TSVs in reduced test time. Finally, we present techniques for recovery of those faulty TSVs in 3D IC.

3D integrated circuit (3D IC) is becoming challenging for increasing power density and design complexity. Due to vertical integration heat dissipation in 3D IC is increased that creates hotspots on chip and hence temperature of the chip is very serious issue. Traditional fan-based cooling technique is insufficient for 3D ICs. Hence inter-die integrated microchannel cooling technique and dummy thermal Through-Silicon-Vias (TSVs) based techniques are used for controlling thermal behaviour of the chip. In this paper, we have proposed two temperature estimation models for 3D IC based on liquid cooled microchannels and thermal TSVs. Experimental results show that thermal simulation using our approach provide same result compared to [1]. For microfluidic cooling, our proposed thermal simulator is much more accurate than proposed model [2] and less than 0.5% error respect to simulation result with COMSOL thermal simulator using the same experimental environment of [2].