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Cheng-Ho Chang

dblp:51/11106 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2012
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test		 0.112012
$2^{n}$ Pattern Run-Length for Test Data Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test
test data compression		 0.112012
$2^{n}$ Pattern Run-Length for Test Data Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012
Electronic design automation › hardware verification and test
test application time reduction		 0.012012
$2^{n}$ Pattern Run-Length for Test Data Compression · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2012

Methods — techniques the papers use, named apart from their topics

run-length encoding · 0.1
YearPublicationVenuePosition
2012 $2^{n}$ Pattern Run-Length for Test Data Compression
abstract
This paper presents a new pattern run-length compression method whose decompressor is simple and easy to implement. It encodes 2|n| runs of compatible or inversely compatible patterns, either inside a single test data segment or across multiple test data segments. Experimental results show that it can achieve an average compression ratio of 67.64% and considerable test application time savings.
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4