This paper presents the hybrid dynamic tree (HDT), a novel adaptive tree-based data structure for representing high-resolution sparse volumes. Roughly speaking, HDTs combine dense volumetric grids with sparse octrees in a way that makes them both more compact and better-suited to GPUs than state-of-the-art alternatives. For our motivating applications in computer-aided design and manufacturing(CAD/CAM), we show 2× reductions in storage on realistic inputs compared to these alternatives, additionally, we show up to 16 fix speedups over multicore CPU implementations on a specific computational bottleneck known as an offset surface computation. Indeed, these combined improvements allow us to perform offsetting on a single node at resolutions well beyond that of the prior work and the capabilities of current commercial packages. And beyond CAD/CAM, HDTs may find applications in 3D geometric modeling problems for a variety of domains, including medical imaging and graphics.

This paper describes the architecture, design, analysis, and simulation and measurement results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built with a 1.5 V, 130 nm process technology and a two-tier 3D stacking technology using 1.2$\micro\hbox{m}$-diameter, 6$\micro \hbox{m}$-height through-silicon vias (TSVs) and$3.4\nbsp\micro\hbox{m}$-diameter face-to-face bond pads. 3D-MAPS consists of a core tier containing 64 cores and a memory tier containing 64 memory blocks. Each core communicates with its dedicated 4KB SRAM block using face-to-face bond pads, which provide negligible data transfer delay between the core and the memory tiers. The maximum operating frequency is 277 MHz and the maximum memory bandwidth is 70.9 GB/s at 277 MHz. The peak measured memory bandwidth usage is 63.8 GB/s and the peak measured power is approximately 4 W based on eight parallel benchmarks.

The emergence of cloud computing has created a demand for more datacenters, which in turn, has led to the substantial consumption of electricity by computing systems and cooling units. Although recently built warehouse-scale datacenters can nearly completely eliminate cooling overhead, small to medium datacenters, which still spend nearly half of their power on cooling, still labor under heavy cooling overhead. Often overlooked by the cloud computing community, these types of datacenters are not in the minority: They are responsible for more than 70% of the entire electrical power used by datacenters. Thus, to tackle the cooling inefficiencies of these datacenters, we propose ambient temperature-aware capping (ATAC), which maximizes power efficiency while minimizing overheating. ATAC senses the ambient temperature of each server and triggers a new performance capping mechanism to achieve 38% savings in cooling power and 7% savings in total power with less than 1% degradation in performance.

Consolidation through live VM migrations is a promising approach to improve server utilization. However, prior consolidation works have focused mostly on the performance impact of migration and neglected the associated energy overhead. Our research finds that energy impact of migration can offset over 12 % of the energy saved through energy-conscious workload packing. To address this limitation of the current state of research, in this paper we devise new schemes to pack applications that targets a joint optimization of energy and performance overhead of VM migrations. Additionally, we develop a statistical workload modeling technique for simulating consolidation problem in enterprise cloud contexts. Our experiments with statistically generated synthetic trace and Google's production trace demonstrate that our schemes can improve energy savings up to 23% compared to state of the art power-aware workload consolidation strategy.